
aPPendix a i/o MaP
s1C33L17 teChniCaL ManuaL
ePson
aP-a-47
AP
I/Omap
0x300B14–0x300B1C
serial interface
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
sRdYCtL1
FiFoint11
FiFoint10
diVMd1
iRtL1
iRRL1
iRMd11
iRMd10
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 #SRDY control
Ch.1 receive buffer full interrupt
timing
Ch.1 async. clock division ratio
Ch.1 IrDA I/F output logic inversion
Ch.1 IrDA I/F input logic inversion
Ch.1 interface mode select
IRMD1[1:0]
I/F mode
reserved
IrDA 1.0
reserved
General I/F
11
10
01
00
11
10
01
00
FIFOINT1[1:0] Receive level
4
3
2
1
0
X
R/W
Writing is disabled
when SIOADV
(D0/0x300B4F) = "0".
Valid only in
asynchronous mode.
00300B14
(B)
1 1/8
0 1/16
1 High mask 0 Normal
1 Inverted
0 Direct
1 Inverted
0 Direct
serial i/F Ch.1
irda register
(pEFSIF1_IRDA)
–
–
BRtRun1
D7–1
D0
reserved
Baud-rate timer Run/Stop control
–
0
–
R/W
0 when being read.
00300B15
(B)
1 Run
0 Stop
serial i/F Ch.1
baud-rate timer
control register
(pEFSIF1_BRTRUN)
0x0 to 0xFF
(BRTRD1[11:0] = 0x0 to 0xFFF)
BRtRd17
BRtRd16
BRtRd15
BRtRd14
BRtRd13
BRtRd12
BRtRd11
BRtRd10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1
baud-rate timer reload data [7:0]
0
R/W
00300B16
(B)
serial i/F Ch.1
baud-rate timer
reload data
register (LsB)
(pEFSIF1_BRTRDL)
–
0x0 to 0xF
(BRTRD1[11:0] = 0x0 to 0xFFF)
–
BRtRd111
BRtRd110
BRtRd19
BRtRd18
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.1
baud-rate timer reload data [11:8]
–
0
–
R/W
0 when being read.
00300B17
(B)
serial i/F Ch.1
baud-rate timer
reload data
register (MsB)
(pEFSIF1_BRTRDM)
0x0 to 0xFF
(BRTCD1[11:0] = 0x0 to 0xFFF)
BRtCd17
BRtCd16
BRtCd15
BRtCd14
BRtCd13
BRtCd12
BRtCd11
BRtCd10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1
baud-rate timer count data [7:0]
0
R
00300B18
(B)
serial i/F Ch.01
baud-rate timer
count data
register (LsB)
(pEFSIF1_BRTCDL)
–
0x0 to 0xF
(BRTCD1[11:0] = 0x0 to 0xFFF)
–
BRtCd111
BRtCd110
BRtCd19
BRtCd18
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.1
baud-rate timer count data [11:8]
–
0
–
R
0 when being read.
00300B19
(B)
serial i/F Ch.1
baud-rate timer
count data
register (MsB)
(pEFSIF1_BRTCDM)
RPnuM12
RPnuM11
RPnuM10
CLKoen1
CLKoL1
MsBseL1
7816Md11
7816Md10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1
number of transmit repetition
Ch.1 clock output enable
Ch.1 clock output forced low
Ch.1 MSB first selection
Serial I/F Ch.1
ISO7816 mode selection
0
R/W
00300B1a
(B)
serial i/F Ch.1
iso7816 mode
control register
(pEFSIF1_7816CTL)
7816MD1[1:0]
Mode
reserved
ISO7816, T = 1
ISO7816, T = 0
Normal I/F
0x0 to 0x7
11
10
01
00
1 Normal
0 Forced low
1 Enabled
0 Disabled
1 MSB first
0 LSB first
–
teR1
D7–1
D0
reserved
Ch.1 ISO7816 transmit error flag
–
0
–
R/W
0 when being read.
Reset by writing 0.
00300B1B
(B)
serial i/F Ch.1
iso7816 mode
status register
(pEFSIF1_7816STA)
–
1 Error
0 Normal
0x0 to 0xFF
(FIDI1[13:0] = 0x0 to 0x3FFF)
Fidi17
Fidi16
Fidi15
Fidi14
Fidi13
Fidi12
Fidi11
Fidi10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1
ISO7816 mode FI/DI ratio [7:0]
0
R/W Valid only in
ISO7816 mode.
00300B1C
(B)
serial i/F Ch.1
iso7816 mode
Fi/di ratio
register (LsB)
(pEFSIF1_FIDIL)