
iiBusModuLes:high-sPeeddMa(hsdMa)
ii-1-30
ePson
s1C33L17teChniCaLManuaL
0x301124–0x301154:hsdMaCh.xLow-ordersourceaddresssetup
Registers(phsx_sadR)
name
address
Registername
Bit
Function
setting
init. R/W
Remarks
sxadRL15
sxadRL14
sxadRL13
sxadRL12
sxadRL11
sxadRL10
sxadRL9
sxadRL8
sxadRL7
sxadRL6
sxadRL5
sxadRL4
sxadRL3
sxadRL2
sxadRL1
sxadRL0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D)Ch.xsourceaddress[15:0]
S)Ch.xmemoryaddress[15:0]
0
R/W
00301124
|
00301154
(hW)
hsdMaCh.x
low-order
sourceaddress
setupregister
(pHSx_SADR)
Note:
D) Dualaddress
mode
S) Single
address
mode
note: Theletter‘x’inbitnames,etc.,denotesachannelnumberfrom0to3.
0x301124 HSDMACh.0Low-OrderSourceAddressSetupRegister(pHS0_SADR)
0x301134 HSDMACh.1Low-OrderSourceAddressSetupRegister(pHS1_SADR)
0x301144 HSDMACh.2Low-OrderSourceAddressSetupRegister(pHS2_SADR)
0x301154 HSDMACh.3Low-OrderSourceAddressSetupRegister(pHS3_SADR)
d[15:0] sxadRL[15:0]:Ch.xsourceaddress[15:0](forstandardmode)
In dual-address mode, these bits are used to specify a source address. In single-address mode, an exter-
nal memory address at the destination or source of transfer is specified.
Use SxADRL[15:0] to set the 16 low-order bits of the address.
Be sure to disable DMA transfers (HSx_EN (D0/0x30112C + 0x10x) = 0) before writing or reading to
and from these registers.
The address is incremented or decremented (as set by SxIN[1:0] (D[13:12]/0x301126 + 0x10x) or
SxID (D4/0x301162 + 0x10x)) according to the transfer data size each time a DMA transfer in the cor-
responding channel is performed.
notes: ThefollowingareascannotbeusedforDMAtransfer:
Dual-addressmode: Area0,Area2
Single-addressmode: Area0,Area1,Area2,Area3,Area6
Single-addressmodedoesnotallowdatatransferbetweenmemorydevices.
Single-address mode does not support the external memory area that is configured for
SDRAM.
Use SxADRL[15:0] (D[15:0]/0x301164 + 0x10x) and SxADRH[15:0] (D[15:0]/0x301166 +
0x10x)forspecifyinganaddressinadvancedmode.