
iXPeRiPheRaLMoDuLes7(usB):usBFunCtionContRoLLeR(usB)
iX-1-108
ePson
s1C33L17teChniCaLManuaL
0x30099C:DMa_Count_hh(DMatransferByteCounterhiGh/hiGh)
0x30099D:DMa_Count_hL(DMatransferByteCounterhiGh/LoW)
0x30099e:DMa_Count_Lh(DMatransferByteCounterLoW/hiGh)
0x30099F:DMa_Count_LL(DMatransferByteCounterLoW/LoW)
name
address
Registername
Bit
setting
init. R/W
Remarks
DMa_Count[31]
DMa_Count[30]
DMa_Count[29]
DMa_Count[28]
DMa_Count[27]
DMa_Count[26]
DMa_Count[25]
DMa_Count[24]
D7
D6
D5
D4
D3
D2
D1
D0
0
R/W
0030099C
(B)
DMa_Count_hh
(DMatransfer
bytecounter
high/high)
DMAtransferbytecounter
DMa_Count[23]
DMa_Count[22]
DMa_Count[21]
DMa_Count[20]
DMa_Count[19]
DMa_Count[18]
DMa_Count[17]
DMa_Count[16]
D7
D6
D5
D4
D3
D2
D1
D0
0
R/W
0030099D
(B)
DMa_Count_hL
(DMatransfer
bytecounter
high/low)
DMAtransferbytecounter
DMa_Count[15]
DMa_Count[14]
DMa_Count[13]
DMa_Count[12]
DMa_Count[11]
DMa_Count[10]
DMa_Count[9]
DMa_Count[8]
D7
D6
D5
D4
D3
D2
D1
D0
0
R/W
0030099e
(B)
DMa_Count_Lh
(DMatransfer
bytecounter
low/high)
DMAtransferbytecounter
DMa_Count[7]
DMa_Count[6]
DMa_Count[5]
DMa_Count[4]
DMa_Count[3]
DMa_Count[2]
DMa_Count[1]
DMa_Count[0]
D7
D6
D5
D4
D3
D2
D1
D0
0
R/W
0030099F
(B)
DMa_Count_LL
(DMatransfer
bytecounter
low/low)
DMAtransferbytecounter
DMa_Count[31:0]
These registers specify the data length in the DMA transfer in units of byte, and displays it. Its setting
can be done as large as up to 0xFFFFFFFF bytes.
When the DMA is set to be in the free run mode by the setting of the CountMode bit of the
DMA_Config_1 register (CountMode = 0), values transmitted by the DMA can be referred at any time.
In this mode, when the DMA Transfer Byte Counter exceeds 0xFFFFFFFF, it returns to 0x00000000
and the DMA_CountUp bit of the DMA_IntStat register is set to 1.
When the DMA is set to be in the countdown mode by the setting of the CountMode bit of the
DMA_Config_1 register (CountMode = 1), specify the total number of transmissions in the DMA
Transfer Byte Counter, set the DMA_Go bit of the DMA_Control register to 1, and then start the DMA
transfer.
In this mode, the DMA Transfer Byte Counter is decreased as much as the data quantity transferred by
the DMA. When it reaches 0x00000000, the DMA ends. In this mode, the remained quantity of the data
to transfer can be referred. Writing into these registers during the DMA transfer is neglected.
For reading these registers, access the DMA_Count_HH, HL, LH and LL registers in this order.