
V PeRiPheRaL MoDuLes 3 (inteRFaCe): i2s inteRFaCe (i2s)
V-4-20
ePson
s1C33L17 teChniCaL ManuaL
i2s FiFo full interrupt (Ch.1)
The I2S CH.1 has an embedded FIFO (24 or 16 bits
× 2 channels (L & R) × 4) for storing four received ste-
reo data. The I2S module can generate interrupts to request the application program to read data in the FIFO
when the received data is written to the FIFO. The I2S CH.1 provides three interrupt modes with differ-
ent interrupt timings: half full interrupt mode, whole full interrupt mode, and one data interrupt mode. Use
I2SINTMD1[1:0] (D[7:6]/pI2S_INT_MOD register) to select an interrupt mode. Furthermore, set I2SINTEN1
(D4/pI2S_INT_MOD register) to 1 to enable the I2S FIFO full interrupt.
i2sintMD1[1:0]: I2S CH.1 Interrupt Mode Select Bits in the I2S Interrupt Mode Select (pI2S_INT_MOD)
Register (D[7:6]/0x00301C18)
i2sinten1: I2S CH.1 Interrupt Enable Bit in the I2S Interrupt Mode Select (pI2S_INT_MOD) Register
(D4/0x00301C18)
Table V.4.7.2 Selecting I2S CH.1 Interrupt Mode
i2sintMD1[1:0]
interrupt Mode
0x3
Reserved
0x2
One data interrupt mode
0x1
Whole full interrupt mode
0x0
Half full interrupt mode
(Default: 0x0)
Whole full interrupt mode
While audio data is being input in this mode, the I2S CH.1 generates an interrupt after four received stereo
data have been written to the FIFO. In other words, the FIFO is full when an interrupt occurs. Therefore, the
application program needs to read four stereo data (24 or 16 bits
× 2 channels (L & R) × 4) from the FIFO
at once after an interrupt occurs.
half full interrupt mode (default)
In this mode, the I2S CH.1 generates an interrupt after two received stereo data have been written to the
FIFO. In this case, the FIFO may be full or it may contain two or three received data (the FIFO status can
be checked using the status bits). The application program needs to read two stereo data (24 or 16 bits
× 2
channels (L & R)
× 2) from the FIFO at once after an interrupt occurs.
one data interrupt mode
In this mode, the I2S CH.1 generates an interrupt after one received stereo data has been written to the
FIFO. In this case, the FIFO may be full or it may contain one to three data (the FIFO status can be checked
using the status bits). The application program needs to read one stereo data (24 or 16 bits
× 2 channels (L
& R)
× 1) from the FIFO at once after an interrupt occurs.