
Vii PeRiPheRaL MoDuLes 5 (anaLoG): a/D ConVeRteR (aDC)
s1C33L17 teChniCaL ManuaL
ePson
Vii-1-5
VII
ADC
setting the input clock
The A/D converter contains a prescaler and the A/D conversion clock can be selected from among the eight
types shown in Table VII.1.4.2 below. Use PSAD[2:0] (D[2:0]/0x300520) for this selection.
PsaD[2:0]:A/DConverterClockDivisionRatioSetupBitsintheA/DClockControlRegister(D[2:0]/0x300520)
TableVII.1.4.2InputClockSelection
PsaD2
1
0
PsaD1
1
0
1
0
PsaD0
1
0
1
0
1
0
1
0
Division ratio
MCLK/256
MCLK/128
MCLK/64
MCLK/32
MCLK/16
MCLK/8
MCLK/4
MCLK/2
(Default:0b000=MCLK/2)
The selected clock is output from the prescaler by writing 1 to PSONAD (D3/0x300520).
PsonaD:A/DConverterClockControlBitintheA/DClockControlRegister(D3/0x300520)
notes: Therecommendedinputclockfrequencyisamaximumof2MHzandaminimumof16kHz.
DonotstartanA/Dconversionwhentheclockoutputfromtheprescaleristurnedoff,anddo
notturnofftheprescaler'sclockoutputwhenanA/Dconversionisunderway.Thiscouldcause
theA/Dconvertertooperateerratically.
selecting analog-conversion start and end channels
Select the channel in which the A/D conversion is to be performed from among the pins (channels) that have
been set for analog input. To enable A/D conversions in multiple channels to be performed successively through
one convert operation, specify the conversion start and conversion end channels using CS[2:0] (D[10:8]/
0x300542) and CE[2:0] (D[13:11]/0x300542) respectively.
note: ThecontrolsectionoftheA/Dconvertersupportseightchannelstoallowfutureexpansion.
Even for channels without analog input, the A/D converter performs the same conversion
performedforchannelswithanaloginputs.
Iftheconversionisperformedforachannelwithoutanaloginput,0x0isstoredinADD[9:0](A/D
ConversionResultRegister).
Todisableconversionfornonexistentchannels,setCS[2:0]toavaluesmallerthanCE[2:0].
Cs[2:0]:A/DConverterStartChannelSetupBitsintheA/DTrigger/ChannelSelectRegister(D[10:8]/0x300542)
Ce[2:0]:A/DConverterEndChannelSetupBitsintheA/DTrigger/ChannelSelectRegister(D[13:11]/0x300542)
TableVII.1.4.3RelationshipbetweenCS/CEandInputChannel
Cs2/Ce2
1
0
Other
Cs1/Ce1
0
1
0
Cs0/Ce0
0
1
0
1
0
Channel selected
AIN4
AIN3
AIN2
AIN1
AIN0
Reserved
Example: Operation of one A/D conversion
CS[2:0] = 0, CE[2:0] = 0: Converted only in AIN0
CS[2:0] = 0, CE[2:0] = 3: Converted in the following order: AIN0
→AIN1→AIN2→AIN3
CS[2:0] = 3, CE[2:0] = 1: Converted in the following order: AIN3
→AIN4→(AIN5)→(AIN6)→(AIN7)→
AIN0
→AIN1
note: Onlyconversion-channelinputpinsthathavebeensetforusewiththeA/Dconvertercanbeset
usingCS[2:0](D[10:8]/0x300542)andCE[2:0](D[13:11]/0x300542).