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Power
i.4.6PrecautionsonPowersupply
Power-onsequence
In order to operate the device normally, supply power in accordance with the following timing.
VDDH, AVDD
VDD, PLVDD
OSC3
#RESET
VDD min.
tVDD
tSTA3
tRST
Figure I.4.6.1 Power-On Sequence
(1) tVDD: Elapsed time until the power supply stabilizes after power-on
Supply power in the following sequence (or simultaneously).
Power-on: VDD and PLVDD (Internal)
→ VDDH and AVDD (I/O) → Apply the input signal
(2) tSTA3: Time at which OSC3 oscillation starts
(3) tRST: Minimum reset pulse width
Time at which the clock supplied to the chip stabilizes plus at least six clocks; Keep the #RESET
signal low.
Power-offsequence
Shut off the power supply in the following sequence (or simultaneously).
Power-off: Turn off the input signal
→ AVDD and VDDH (I/O) → PLVDD and VDD (Internal)
Latch-up
The CMOS device may be in the latch-up condition. This is the phenomenon caused by conduction of the
parasitic PNPN junction (thyristor) contained in the CMOS IC, resulting in a large current between VDD and
VSS and leading to breakage.
Latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows
into the internal element, or when the voltage at the VDD pin exceeds the rated value and the internal element is
in the breakdown condition. In the latter case, even if the application of a voltage exceeding the rated value is
instantaneous, the current remains high between VDD and VSS once the device is in the latch-up condition. As
this may result in heat generation or smoking, the following points must be taken into consideration:
(1) The voltage level at the input / output must not exceed the range specified in the electrical characteristics.
In other words, it must be below the power-supply voltage and above VSS. The power-on timing should also
be taken into consideration.
(2) Abnormal noise must not be applied to the device.
(3) The potential at the unused input should be fixed at VDD, VDDH, AVDD, or VSS.
(4) No outputs should be shorted.