
iiBusModuLes:inteLLigentdMa(idMa)
ii-2-6
ePson
s1C33L17teChniCaLManuaL
dsinC[2:0]=001: addressdecrementwithoutinitialization(addressisnotreset)
The destination address is decremented by an amount equal to the data size set by DATSIZ when one data
transfer is completed. The address that has been decremented during transfer does not return to the initial
value.
dsinC[2:0]=010: addressincrementwithinitialization
(addressisresetinsuccessiveorblocktransfermode)
The destination address is incremented by an amount equal to the data size set by DATSIZ when one
data transfer is completed. In single transfer mode, the address that has been incremented during transfer
does not return to the initial value. In successive transfer modes, the incremented address returns to the
initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the
incremented address returns to the initial value when the block transfer is completed.
dsinC[2:0]=100: addressdecrementwithinitialization
(addressisresetinsuccessiveorblocktransfermode)
The destination address is decremented by an amount equal to the data size set by DATSIZ when one
data transfer is completed. In single transfer mode, the address that has been decremented during transfer
does not return to the initial value. In successive transfer modes, the decremented address returns to the
initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the
decremented address returns to the initial value when the block transfer is completed.
dsinC[2:0]=otherthanabove:settingsareprohibited
note: Insingletransfermode,theaddressdoesnotreturntotheinitialvalueevenifaconditionwith
addressinitializationisspecified.
dMod[1:0]:transfermode(d[5:4]/1stword)
Use these bits to set the desired transfer mode.
The transfer modes are outlined below (to be detailed later):
dMod[1:0]=00:singletransfermode
In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data
of the size set by DATSIZ. If data transfer need to be performed a number of times as set by the transfer
counter, an equal number of triggers are required.
dMod[1:0]=01:successivetransfermode
In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer
counter. The transfer counter is decremented to 0 each time data is transferred.
dMod[1:0]=10:Blocktransfermode
In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of
the size set by BLKLEN. If a block transfer need to be performed a number of times as set by the transfer
counter, an equal number of triggers are required.
dMod[1:0]=11:settingsareprohibited
dinten:end-of-transferinterruptenable(d0/1stword)
If this bit is left set (= 1), when the transfer counter reaches 0, an interrupt request to the CPU is generated
based on the cause-of-interrupt flag by which IDMA has been invoked.
If this bit is 0, no interrupt request to the CPU is generated even when the transfer counter has reached 0.
tC[19:0]:transfercounter(d[31:12]/2ndword)
In block transfer mode, a transfer count can be specified using up to 20 bits. Set this value here.
In single transfer and successive transfer modes, a transfer count can be specified using up to 32 bits. Set a
20-bit high-order value here.