
is1C33L17sPeCifiCations:PowersuPPLy
i-4-2
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i.4.2operatingvoltage(vDD,vss)
The core CPU and internal logic circuits operate with a voltage supplied between the VDD and VSS pins. The
following operating voltage can be used:
VDD = 1.65 V to 1.95 V (1.8 V
± 0.15 V, VSS = GND)
or
VDD = 1.70 V to 1.90 V (1.8 V
± 0.10 V, VSS = GND) when the ceramic oscillator circuit is used
note: The S1C33L17 QFP package has six VDD pins and seven VSS pins; the PFBGA package has 12
VDD pins and 16 VSS pins. Be sure to supply the operating voltage to all the pins. Do not open any of
them.
i.4.3PowersupplyforPLL(PLvDD,PLvss)
The PLL power supply pins (PLVDD, PLVSS) are provided separately from the VDD and VSS pins in order that the
digital circuits do not affect the PLL circuit. Supply the same voltage level as the VDD to the PLVDD pin.
PLVDD = VDD, PLVSS = VSS
Noise on the PLL power lines decrease the PLL output precision, so use a stabilized power supply and make the
board pattern with consideration given to that.
i.4.4Powersupplyfori/ointerface(vDDh)
The VDDH voltage is used for interfacing with external I/O signals. For the output interface of the S1C33L17, the
VDDH voltage is used as high level and the VSS voltage as low level. The VSS pin is used for the ground common
with VDD. The following voltage is enabled for VDDH:
VDDH =2.70 V to 3.60 V (VSS = GND) when the USB function controller is not used
or
VDDH =3.00 V to 3.60 V (3.3 V
± 0.3 V, VSS = GND) when the USB function controller is used
notes: The S1C33L17 QFP package has six VDDH pins; the PFBGA package has 12 VDDH pins. Be
sure to supply the operating voltage to all the pins. Do not open any of them.
When an external clock is input to the MCLKI or RTC_CLKI pin, the clock signal level must be
VDD.
i.4.5PowersupplyforanalogCircuits(avDD)
The analog power supply pin (AVDD) is provided separately from the VDD and VDDH pins in order that the digital
circuits do not affect the analog circuit (A/D converter). The AVDD pin is used to supply an analog power voltage
and the VSS pin is used as the analog ground.
The following voltage is enabled for AVDD:
AVDD = 2.70 V to 3.60 V (3.0/3.3 V
± 0.3 V, VSS = GND)
note: Be sure to supply VDDH to the AVDD pin when the analog circuit is not used.
Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make
the board pattern with consideration given to that.