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V-2-7
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UART
Data receive control
The receiver activates by setting the RXEN bit to 1 and is ready to receive data sent from an external serial
device.
When an external serial device has sent a start bit, the receiver detects its low level and starts following data bit
sampling. The data bits are sampled at the rising edge of the sampling clock and received in the receive shift
register assuming that the first data bit is LSB. After the MSB is received in the shift register, the received data
is loaded to the receive data buffer. At the same time, the receiver performs a parity check with the parity bit
received after the MSB if parity check is enabled.
The receive data buffer is a two-byte FIFO and can receive data until it becomes full.
The received data in the buffer can be read from the UART_RXD register (0x00300B21). The older data is read
out first and cleared by reading.
uaRt_RXD: UART Receive Data Register (0x00300B21)
The receiver provides two buffer status flags, RDRY (D1/UART_STATUS register) and RD2B (D3/
UART_STATUS register).
RDRY: Receive Data Ready Flag in the UART Status (UART_STATUS) Register (D1/0x00300B22)
RD2B: Second Byte Receive Flag in the UART Status (UART_STATUS) Register (D3/0x00300B22)
The RDRY flag indicates that the receive data buffer contains the received data. The RD2B flag indicates that
the receive data buffer is full.
(1) RDRY = 0, RD2B = 0
No data has been received. Therefore, it is not necessary to read the receive data buffer.
(2) RDRY = 1, RD2B = 0
One data has been received. Read the receive data buffer once. This reading clears the read data and resets
the RDRY flag. The buffer status returns to (1) above.
If the receive data buffer is read twice, the second read value is invalid data.
(3) RDRY = 1, RD2B = 1
Two data have been received. Read the receive data buffer twice. The receive data buffer outputs the older
received data in the first reading. This reading clears the read data and resets the RD2B flag. The buffer
status goes to (2) above. The latest received data is output in the second reading. The buffer status returns to
(1) above after reading twice.
The shift register can receive one more data even if the receive data buffer is full. If an additional data is
sent from the external serial device in this status, an overrun error occurs and the data in the shift register
is overwritten with the new data. Therefore, be sure to read the receive data buffer before an overrun error
occurs. Refer to Section V.2.6 for the overrun error.
By reading these flags, the application program can check how many data have been received.
Furthermore, the UART can generate a receive data buffer full interrupt when data is received in the receive
data buffer. This interrupt can be used to read the received data. A receive data buffer full interrupt occurs when
one data has been received in the receive data buffer (status (2) above) by default. This may be changed by
setting the RBFI bit (D1/UART_CTL register) to 1 so that the interrupt will occur when two data have been
received in the received data buffer.
RBFi: Receive Buffer Full Interrupt Condition Setup Bit in the UART Control (UART_CTL) Register (D1/
0x00300B23)
In addition to the flags above, three receive error flags are provided. Refer to Section V.2.6 for these flags and
details of receive errors.