
aPPendix a i/o MaP
aP-a-6
ePson
s1C33L17 teChniCaL ManuaL
0x300284–0x300293
interrupt Controller
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
–
Fstx1
FsRx1
FseRR1
Fstx0
FsRx0
FseRR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
–
X
–
R/W
0 when being read.
00300286
(B)
1 Occurred
0 Not occurred
serial i/F
Ch.0–1
interrupt cause
flag register
(pINT_FSIF01)
–
FP7
FP6
FP5
FP4
FRtC
Fade
FadC
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
RTC
A/D conversion completion
A/D out-of-range
–
X
–
R/W
0 when being read.
00300287
(B)
1 Occurred
0 Not occurred
Port input 4–7,
RtC, a/d
interrupt cause
flag register
(pINT_FP47_FRTC
_FAD)
–
FLCdC
–
D7–2
D1
D0
reserved
LCDC frame end
reserved
–
X
–
R/W
–
0 when being read.
00300288
(B)
LCdC interrupt
cause flag
register
(pINT_FLCDC)
–
1 Occurred
0 Not occurred
–
–
FsPitx
FsPiRx
–
Fstx2
FsRx2
FseRR2
D7–6
D5
D4
D3
D2
D1
D0
reserved
SPI transmit DMA
SPI receive DMA
reserved
SIF Ch.2 transmit buffer empty
SIF Ch.2 receive buffer full
SIF Ch.2 receive error
–
X
–
X
–
R/W
–
R/W
0 when being read.
00300289
(B)
1 Occurred
0 Not occurred
serial i/F Ch.2,
sPi interrupt
cause flag
register
(pINT_FSIF2_FSPI)
–
1 Occurred
0 Not occurred
R16tC0
R16tu0
RhdM1
RhdM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
HSDMA Ch.1
HSDMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
00300290
(B)
1 IDMA
request
0 Interrupt
request
Port input 0–3,
hsdMa Ch.0–1,
16-bit timer 0
idMa request
register
(pIDMAREQ_RP03
_RHS_R16T0)
–
R16tC3
R16tu3
R16tC2
R16tu2
R16tC1
R16tu1
D7–6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
–
0
–
R/W
0 when being read.
00300291
(B)
1 IDMA
request
0
–
16-bit timer 1–3
idMa request
register
(pIDMAREQ_
R16T13)
Rstx0
RsRx0
–
D7
D6
D5–0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
reserved
0
–
R/W
–
0 when being read.
00300292
(B)
1 IDMA
request
0 Interrupt
request
serial i/F Ch.0
idMa request
register
(pIDMAREQ_
RSIF0)
–
RP7
RP6
RP5
RP4
–
Rade
Rstx1
RsRx1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D conversion completion
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
–
0
R/W
–
R/W
0 when being read.
00300293
(B)
1 IDMA
request
0 Interrupt
request
1 IDMA
request
0 Interrupt
request
–
serial i/F Ch.1,
a/d,
port input 4–7
idMa request
register
(pIDMAREQ_RSIF1
_RAD_RP47)