
aPPendix a i/o MaP
s1C33L17 teChniCaL ManuaL
ePson
aP-a-75
AP
I/Omap
0x301a30–0x301a48
LCd Controller
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
–
FPFstPo9
FPFstPo8
FPFstPo7
FPFstPo6
FPFstPo5
FPFstPo4
FPFstPo3
FPFstPo2
FPFstPo1
FPFstPo0
–
FPFsto9
FPFsto8
FPFsto7
FPFsto6
FPFsto5
FPFsto4
FPFsto3
FPFsto2
FPFsto1
FPFsto0
D31–26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15–10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
FPFRAME pulse stop offset
reserved
FPFRAME pulse start offset
–
0
–
0
–
R/W
–
R/W
0 when being read.
*1: For HR-TFT
0x0 must be set
for STN panels.
0 when being read.
(
*1)
00301a30
(W)
FPFRaMe
pulse offset
register
(pLCDC_FO)
–
Stop offset = FPFSTPO [pixels]
–
Start offset = FPFSTO [pixels]
–
CtL1CtL
PReset
FPsPoL
CtLsWaP
D31–4
D3
D2
D1
D0
reserved
TFT_CTL1 control
TFT_CTL0–2 preset enable
FPSHIFT polarity
TFT_CTL0/TFT_CTL1 swap
–
0
–
R/W
0 when being read.
For HR-TFT
0x0 must be set for
STN panels.
00301a40
(W)
hR-tFt special
output register
(pLCDC_TSO)
–
0
1 Program
Toggle/line
0
1 Program
Preset
0
1 Falling
Rising
0
1 Swap
Not swap
–
CtL1stP9
CtL1stP8
CtL1stP7
CtL1stP6
CtL1stP5
CtL1stP4
CtL1stP3
CtL1stP2
CtL1stP1
CtL1stP0
–
CtL1st9
CtL1st8
CtL1st7
CtL1st6
CtL1st5
CtL1st4
CtL1st3
CtL1st2
CtL1st1
CtL1st0
D31–26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15–10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
TFT_CTL1 pulse stop offset
TFT_CTL1 pulse width
= (CTL1STP - CTL1ST +1) Ts
reserved
TFT_CTL1 pulse start offset
–
0
–
0
–
R/W
–
R/W
0 when being read.
*2: For HR-TFT
This register is
enabled when
PRESET = 1.
0 when being read.
(
*2)
00301a44
(W)
tFt_CtL1
pulse register
(pLCDC_TC1)
–
Stop offset = CTL1STP + 1
[pixels]
–
Start offset = CTL1ST [pixels]
–
CtL0stP9
CtL0stP8
CtL0stP7
CtL0stP6
CtL0stP5
CtL0stP4
CtL0stP3
CtL0stP2
CtL0stP1
CtL0stP0
–
CtL0st9
CtL0st8
CtL0st7
CtL0st6
CtL0st5
CtL0st4
CtL0st3
CtL0st2
CtL0st1
CtL0st0
D31–26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15–10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
TFT_CTL0 pulse stop offset
TFT_CTL0 pulse width
= (CTL0STP - CTL0ST +1) Ts
reserved
TFT_CTL0 pulse start offset
–
0
–
0
–
R/W
–
R/W
0 when being read.
*2: For HR-TFT
This register is
enabled when
PRESET = 1.
0 when being read.
(
*2)
00301a48
(W)
tFt_CtL0
pulse register
(pLCDC_TC0)
–
Stop offset = CTL0STP + 1
[pixels]
–
Start offset = CTL0ST [pixels]