
is1C33L17sPeCifiCations:PinDesCriPtion
s1C33L17teChniCaLManuaL
ePson
i-3-1
I
Pin
I.3 Pin Description
i.3.1Pinarrangement
The S1C33L17 comes in a TQFP24-144pin or PFBGA-180pin plastic package.
i.3.1.1QfPPackagePinarrangement(s1C33L17f)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
(P55/CarD0/fPDat14)#Ce9
(P46/tft_CtL2)a18
(P45/fPDat11)a19
(P44/fPDat10)a20
(P43/fPDat9)a21
(P42/fPDat8)a22
v
ss
(CarD2/#DMareQ0/fPDat12)P30
(CarD3/#DMareQ1/fPDat13)P31
(CarD4/#DMareQ2/fPDat14)P32
(CarD5/#DMareQ3/fPDat15)P33
(sin0/#DMaaCk2)P00
(sout0/#DMaaCk3)P01
(#sCLk0/#DMaenD2)P02
(#srDy0/#DMaenD3)P03
v
DDh
(sin1/i2s_sDo)P04
(sout1/i2s_ws_o/i2s_ws_i)P05
(#sCLk1/i2s_sCk_o/i2s_sCk_i)P06
(#srDy1/i2s_MCLk_o)P07
(i2s_sDi/sin0/#DMaenD0)P10
(i2s_ws_i/sout0/#DMaenD1)P11
v
DD
(i2s_sCk_i/#sCLk0/#DMaaCk0)P12
(i2s_MCLk_i/#srDy0/#DMaaCk1)P13
(tM2/sin1)P14
(P15/tM3/sout1/tft_CtL0)Dst0
(P16/CarD0/#sCLk1/tft_CtL3)Dst1
(P17/CarD1/#srDy1/tft_CtL2)DPCo
v
DDh
(P34)Dsio
(P36)Dst2
(P35)DCLk
(#wait/eXCL2)P64
(sDi/fPDat8)P65
(sDo/fPDat9)P66
P25(#sDwe)
P24(#sDCas)
P23(#sDras/tft_CtL1)
v
DDh
P22(#sDCs)
sDCLk(P21)
P20(sDCke)
v
ss
D15
D14
D13
D12
v
DD
D11
D10
D9
D8
v
DDh
D7
D6
D5
D4
v
DD
D3
D2
D1
D0
v
ss
P63(fPDat13/wDt_CLk/#wDt_nMi)
P62(fPDat12/#aDtrg/CMu_CLk)
P61(sout2/fPDat14/eXCL1)
P60(sin2/fPDat15/eXCL0)
usBvBus
usBDP
usBDM
#nMi
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
#reset
P97(fPDat7)
P96(fPDat6)
P95(fPDat5)
P94(fPDat4)
vDDh
P93(fPDat3)
P92(fPDat2/sPiCLk)
P91(fPDat1/sDo)
P90(fPDat0/sDi)
vss
MCLko
MCLki
vDD
P85(tM1)
P84(tM0/fPDat11)
P83(fPDrDy/tft_CtL1/BCLk)
P82(fPshift)
P81(fPLine)
P80(fPfraMe)
P70(ain0)
P71(ain1)
P72(ain2)
P73(ain3/i2s_MCLk_eXt)
P74(ain4/eXCL3)
avDD
Boot1
test0
PLvDD
vCP
PLvss
vss
rtC_CLko
rtC_CLki
vDD
P67(sPi_CLk/fPDat10)
(DQML)P26
(DQMh)P27
a14
a15
a16/DQML
a17/DQMh
(P53/sDa10)#Ce7
a0/#BsL
vss
a1
a2
a3
a4
a5
vDD
a6
a7
a8
a9
vDDh
a10
(P47)a11
a12
a13
(P41/fPDat13/#sDras)a23
(P40/fPDat12/#sDCas)a24
vss
(P57)#Ce10
#rD
#wrL
#wrh/#Bsh
(P56)#Ce11
(BCLk/#Ce6/CMu_CLk)P52
(P50/CarD0)#Ce4
(P51/CarD1)#Ce5
(P54/CarD1/fPDat15)#Ce8
Figure I.3.1.1.1 Pin Arrangement (TQFP24-144pin)