
ViiiPeRiPheRaLMoDuLes6(LCD):LCDContRoLLeR(LCDC)
Viii-1-34
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s1C33L17teChniCaLManuaL
Viii.1.8Powersave
The LCD controller has two types of power-save modes. Use PSAVE[1:0] (D[1:0]/0x301A04) to set power-save
modes.
*PsaVe[1:0]:PowerSaveModeSelectBitsintheStatusandPowerSaveConfigurationRegister(D[1:0]/0x301A04)
TableVIII.1.8.1SettingsofPower-SaveModes
PsaVe1
1
0
PsaVe0
1
0
1
0
Mode
Normaloperation
Dozemode
Reserved
Power-savemode
Power-savemode
When the LCD controller enters this mode, all LCD signal output pins are dropped low, with the LCD panel
placed in power-down mode. All operations of the LCD controller, other than accessing of its control registers
and look-up tables are disabled.
The LCD controller is placed in power-save mode by setting PSAVE (D[1:0]/0x301A04) to 0b00.
The LCD controller is taken out of power-save mode by setting PSAVE (D[1:0]/0x301A04) to 0b11.
Dozemode
Doze mode is a power-save mode designed for use with built-in RAM type or self-refresh type LCD panels.
These panels do no need to send data constantly in order to refresh the display of the same image. The LCD
controller can be set in doze mode during this period. In doze mode, the FPDAT and FPSHIFT signals are fixed
low so that no access to the display memory occurs. Although the power-saving effects are not as significant as
in power-save mode, this mode helps reduce the current consumption in the LCD panel while keeping the dis-
play on.
Comparisonofpower-savemodes
The differences between power-save modes are summarized in Table VIII.1.8.2.
TableVIII.1.8.2DifferencesbetweenPower-SaveModes
item
AccessingI/Oregisters
Accessinglook-uptable
AccessingVRAM
Display(STNpanels)
Display(HR-TFTpanels)
LCDCdisplay-data-fetchoperation
FPDAT[11:0]signals(STN,HR-TFTpanels)
FPSHIFTsignal(STNpanels)
FPLINE,FPFRAME,FPDRDYsignals(STN
panels)
FPSHIFTsignal(HR-TFTpanels)
whenFPSPOL(D1/0x301A40)=0
FPSHIFTsignal(HR-TFTpanels)
whenFPSPOL(D1/0x301A40)=1
FPFRAMEsignal(HR-TFTpanels)
whenFPFPOL(D7/0x301A2C)=0
FPFRAMEsignal(HR-TFTpanels)
whenFPFPOL(D7/0x301A2C)=1
FPLINEsignal(HR-TFTpanels)
whenFPLPOL(D7/0x301A28)=0
FPLINEsignal(HR-TFTpanels)
whenFPLPOL(D7/0x301A28)=1
TFT_CTL1signal* (HR-TFTpanels)
whenCTL1ST[9:0](D[9:0]/0x301A44)=0
TFT_CTL1signal* (HR-TFTpanels)
whenCTL1ST[9:0](D[9:0]/0x301A44)
≠0
TFT_CTL0,TFT_CTL2,TFT_CTL3
signals(HR-TFTpanels)
normal
Enabled
Active
Power-savemode
Enabled
Inactive
Low
High
Low
High
Low
High
Low
High
Low
LCDCdisabled
Disabled
Enabled
Inactive
Low
Dozemode
Enabled
Active
Inactive
Low
Active
High
Low
Active
* TheTFT_CTL1signalisconfiguredwithCTL1CTL(D3/0x301A40)=1,PRESET(D2/0x301A40)=1,and
CTLSWAP(D0/0x301A40)=0.