
iiBusModuLes:high-sPeeddMa(hsdMa)
ii-1-40
ePson
s1C33L17teChniCaLManuaL
0x301164–0x301196:hsdMaCh.xsourceaddresssetupRegisters
(phsx_ad_sadR)foradVmode
name
address
Registername
Bit
Function
setting
init. R/W
Remarks
sxadRL15
sxadRL14
sxadRL13
sxadRL12
sxadRL11
sxadRL10
sxadRL9
sxadRL8
sxadRL7
sxadRL6
sxadRL5
sxadRL4
sxadRL3
sxadRL2
sxadRL1
sxadRL0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D)Ch.xsourceaddress[15:0]
S)Ch.xmemoryaddress[15:0]
0
R/W
00301164
|
00301194
(hW)
hsdMaCh.x
low-order
sourceaddress
setupregister
(pHSx_AD_SADR)
forADVmode
Note:
D) Dualaddress
mode
S) Single
address
mode
sxadRh15
sxadRh14
sxadRh13
sxadRh12
sxadRh11
sxadRh10
sxadRh9
sxadRh8
sxadRh7
sxadRh6
sxadRh5
sxadRh4
sxadRh3
sxadRh2
sxadRh1
sxadRh0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D)Ch.xsourceaddress[31:16]
S)Ch.xmemoryaddress[31:16]
0
R/W
00301166
|
00301196
(hW)
hsdMaCh.x
high-order
sourceaddress
setupregister
forADVmode
Note:
D) Dualaddress
mode
S) Single
address
mode
notes: Thisregisteriseffectiveonlyinadvancedmode(HSDMAADV(D0/0x30119C)=1).
Theletter‘x’inbitnames,etc.,denotesachannelnumberfrom0to3.
0x301164 HSDMACh.0Low-OrderSourceAddressSetupRegister(pHS0_AD_SADR)
0x301166 HSDMACh.0High-OrderSourceAddressSetupRegisterforADVmode
0x301174 HSDMACh.1Low-OrderSourceAddressSetupRegister(pHS1_AD_SADR)
0x301176 HSDMACh.1High-OrderSourceAddressSetupRegisterforADVmode
0x301184 HSDMACh.2Low-OrderSourceAddressSetupRegister(pHS2_AD_SADR)
0x301186 HSDMACh.2High-OrderSourceAddressSetupRegisterforADVmode
0x301194 HSDMACh.3Low-OrderSourceAddressSetupRegister(pHS3_AD_SADR)
0x301196 HSDMACh.3High-OrderSourceAddressSetupRegisterforADVmode
d[15:0]/0x301164–0x301194sxadRL[15:0]:Ch.xLow-ordersourceaddress[15:0]
d[15:0]/0x301166–0x301196sxadRh[15:0]:Ch.xhigh-ordersourceaddress[31:16]
In dual-address mode, these bits are used to specify a 32-bit source address. In single-address mode, a
32-bit external memory address at the destination or source of transfer is specified.
Be sure to disable DMA transfers (HSx_EN (D0/0x30112C + 0x10x) = 0) before writing or reading to
and from these registers.
The address is incremented or decremented (as set by SxIN[1:0] (D[13:12]/0x301126 + 0x10x) or
SxID (D4/0x301162 + 0x10x)) according to the transfer data size each time a DMA transfer in the cor-
responding channel is performed.