
V PeRiPheRaL MoDuLes 3 (inteRFaCe): GeneRaL-PuRPose seRiaL inteRFaCe (eFsio)
V-1-4
ePson
s1C33L17 teChniCaL ManuaL
V.1.1.4 serial interface operating Clock
The serial interface use the clocks generated by the CMU as the operating clock. Furthermore, each channel uses
the data transfer clock generated by the baud-rate timer embedded in the EFSIO module.
Controlling the supply of the clock for accessing eFsio
The SAPB bus interface clock (= MCLK) is supplied to the serial interface with default settings. It can be
turned off using EFSIOSAPB_CKE (D5/0x301B04) to reduce the amount of power consumed on the chip if all
the serial interface functions are not used.
eFsiosaPB_CKe: EFSIO SAPB I/F Clock Control Bit in the Gated Clock Control Register 1 (D5/0x301B04)
Setting EFSIOSAPB_CKE (D5/0x301B04) to 0 (1 by default) turns off the clock supply to the serial interface.
When the clock supply is turned off, the serial interface control registers cannot be accessed.
For details on how to set and control clocks, see Section III.1, “Clock Management Unit (CMU).”
Clock for baud-rate timer and interface
The data transfer clock is generated by the baud-rate timer embedded in each channel. The baud-rate timer op-
erating clock (= MCLK) is supplied separately with the SAPB bus interface clock shown above. Although this
clock cannot be turned off while the S1C33L17 is running, this clock can be automatically turned off in HALT
mode (see Section III.1.9.2) by setting EFSIOBR_HCKE (D25/0x301B04) to 0 (default: on).
eFsioBR_hCKe: EFSIO Baud Rate Clock Control (HALT) Bit in the Gated Clock Control Register 1
(D25/0x301B04)
Refer to Section V.1.2 for the baud-rate timer.
Clock state in standby mode
The clock supply to the serial interface stops depending on type of standby mode.
HALT mode: The SAPB bus interface clock is supplied the same way as in normal mode (it can be stopped
before entering HALT mode).
The baud-rate timer clock can be automatically stopped in HALT mode.
SLEEP mode: The SAPB bus interface clock and baud-rate timer clock stop.
Therefore, the serial interface also stops operating in SLEEP mode.
note: The Gated Clock Control Register 1 (0x301B04) is write-protected. Write protection of this and
other CMU control registers at addresses 0x301B00 to 0x301B14 to be rewritten must be re-
moved by writing 0x96 to the Clock Control Protect Register (0x301B24). Since unnecessary
rewrites to addresses 0x301B00 to 0x301B14 could cause the system to operate erratically, make
sure the data set in the Clock Control Protect Register (0x301B24) is other than 0x96, unless re-
writing said registers.