
aPPendix a i/o MaP
aP-a-46
ePson
s1C33L17 teChniCaL ManuaL
0x300B07–0x300B13
serial interface
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
–
0x0 to 0xF
(BRTRD0[11:0] = 0x0 to 0xFFF)
–
BRtRd011
BRtRd010
BRtRd09
BRtRd08
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.0
baud-rate timer reload data [11:8]
–
0
–
R/W
0 when being read.
00300B07
(B)
serial i/F Ch.0
baud-rate timer
reload data
register (MsB)
(pEFSIF0_BRTRDM)
0x0 to 0xFF
(BRTCD0[11:0] = 0x0 to 0xFFF)
BRtCd07
BRtCd06
BRtCd05
BRtCd04
BRtCd03
BRtCd02
BRtCd01
BRtCd00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0
baud-rate timer count data [7:0]
0
R
00300B08
(B)
serial i/F Ch.0
baud-rate timer
count data
register (LsB)
(pEFSIF0_BRTCDL)
–
0x0 to 0xF
(BRTCD0[11:0] = 0x0 to 0xFFF)
–
BRtCd011
BRtCd010
BRtCd09
BRtCd08
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.0
baud-rate timer count data [11:8]
–
0
–
R
0 when being read.
00300B09
(B)
serial i/F Ch.0
baud-rate timer
count data
register (MsB)
(pEFSIF0_BRTCDM)
0x0 to 0xFF(0x7F)
txd17
txd16
txd15
txd14
txd13
txd12
txd11
txd10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 transmit data
TXD17(16) = MSB
TXD10 = LSB
X
R/W 7-bit asynchronous
mode does not use
TXD17.
00300B10
(B)
serial i/F Ch.1
transmit data
register
(pEFSIF1_TXD)
0x0 to 0xFF(0x7F)
Rxd17
Rxd16
Rxd15
Rxd14
Rxd13
Rxd12
Rxd11
Rxd10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 receive data
RXD17(16) = MSB
RXD10 = LSB
X
R
7-bit asynchronous
mode does not use
RXD17 (fixed at 0).
00300B11
(B)
serial i/F Ch.1
receive data
register
(pEFSIF1_RXD)
Rxd1nuM1
Rxd1nuM0
tend1
FeR1
PeR1
oeR1
tdBe1
RdBF1
D7
D6
D5
D4
D3
D2
D1
D0
Number of Ch.1 receive data
in FIFO
Ch.1 transmit-completion flag
Ch.1 framing error flag
Ch.1 parity error flag
Ch.1 overrun error flag
Ch.1 transmit data buffer empty
Ch.1 receive data buffer full
0
1
0
R
R/W
R
Reset by writing 0.
00300B12
(B)
1 Error
0 Normal
1 Transmitting 0 End
1 Error
0 Normal
1 Error
0 Normal
1 Empty
0 Not empty
1 Full
0 Not full
serial i/F Ch.1
status register
(pEFSIF1_STATUS)
RXD1NUM[1:0] Number of data
4
3
2
1 or 0
11
10
01
00
txen1
Rxen1
ePR1
PMd1
stPB1
ssCK1
sMd11
sMd10
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transmit enable
Ch.1 receive enable
Ch.1 parity enable
Ch.1 parity mode select
Ch.1 stop bit select
Ch.1 input clock select
Ch.1 transfer mode select
SMD1[1:0]
Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
X
R/W
Valid only in
asynchronous mode.
00300B13
(B)
serial i/F Ch.1
control register
(pEFSIF1_CTL)
1 Enabled
0 Disabled
1 Enabled
0 Disabled
1 With parity 0 No parity
1 Odd
0 Even
1 2 bits
0 1 bit
1 #SCLK1
0 Internal clock
11
10
01
00