
aPPendix a i/o MaP
aP-a-68
ePson
s1C33L17 teChniCaL ManuaL
0x301500–0x301510
sRaM Controller
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
–
Ce9BCLK
Ce9hoLd2
Ce9hoLd1
Ce9hoLd0
–
Ce11stuP
Ce4stuP
BCLK
D31–8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
#CE9 area BCLK divide control
#CE9 area output disable time
reserved
#CE11 setup time
#CE4 setup time
BCLK divide control
–
1
0
–
0
1
–
R/W
–
R/W
0 when being read.
00301500
(W)
BCLK and
setup time
control register
(pSRAMC_BCLK
_SETUP)
1 No setup time 0 +1 BCLK
–
0 to 7
–
1 No setup time 0 +1 BCLK
1 SRAMC_CLK
× 1/2 0 SRAMC_CLK × 1
1 SRAMC_CLK
× 1/2 0 SRAMC_CLK × 1
–
Ce11Wait2
Ce11Wait1
Ce11Wait0
Ce10Wait3
Ce10Wait2
Ce10Wait1
Ce10Wait0
Ce9Wait3
Ce9Wait2
Ce9Wait1
Ce9Wait0
Ce8Wait3
Ce8Wait2
Ce8Wait1
Ce8Wait0
Ce7Wait3
Ce7Wait2
Ce7Wait1
Ce7Wait0
Ce6Wait3
Ce6Wait2
Ce6Wait1
Ce6Wait0
Ce5Wait3
Ce5Wait2
Ce5Wait1
Ce5Wait0
Ce4Wait3
Ce4Wait2
Ce4Wait1
Ce4Wait0
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Number of #CE11 static wait
cycles
reserved
Number of #CE10 static wait
cycles
reserved
Number of #CE9 static wait
cycles
reserved
Number of #CE8 static wait
cycles
reserved
Number of #CE7 static wait
cycles
reserved
Number of #CE6 static wait
cycles
reserved
Number of #CE5 static wait
cycles
reserved
Number of #CE4 static wait
cycles
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
0 when being read.
00301504
(W)
Wait control
register
(pSRAMC_SWAIT)
–
0 to 7
–
0 to 7
–
0 to 7
–
0 to 7
–
0 to 7
–
0 to 7
–
0 to 7
–
0 to 7
–
Ce11siZe1
Ce11siZe0
–
Ce9siZe1
Ce9siZe0
Ce8siZe1
Ce8siZe0
Ce7siZe1
Ce7siZe0
Ce6siZe1
Ce6siZe0
Ce5siZe1
Ce5siZe0
Ce4siZe1
Ce4siZe0
D31–16
D15
D14
D13–12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
#CE11 device size
reserved
#CE9 device size
#CE8 device size
#CE7 device size
#CE6 device size
#CE5 device size
#CE4 device size
–
0
1
–
0
1
0
1
0
1
0
1
0
1
0
1
–
R/W
–
R/W
0 when being read.
00301508
(W)
device size
setup register
(pSRAMC_SLV
_SIZE)
–
(See below)
–
CExSIZE[1:0]
Size
reserved
8 bits
16 bits
reserved
11
10
01
00
–
Ce11tYPe
Ce10tYPe
Ce9tYPe
Ce8tYPe
Ce7tYPe
Ce6tYPe
Ce5tYPe
Ce4tYPe
D31–8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
#CE11 device type
#CE10 device type
#CE9 device type
#CE8 device type
#CE7 device type
#CE6 device type
#CE5 device type
#CE4 device type
–
0
–
R/W
0 when being read.
0030150C
(W)
device type
setup register
(pSRAMC_A0_BSL)
–
1 BSL
0 A0
–
a6LoC
D31–1
D0
reserved
Area 6 location setup
–
0
–
R/W
0 when being read.
00301510
(W)
area location
setup register
(pSRAMC_ALS)
–
1 External
0 Internal