
is1C33L17sPeCifiCations:MeMoryMaP
i-6-4
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s1C33L17teChniCaLManuaL
i.6.3area1(specificroMforfirmware)
Area 1 contains a 64K-byte mask ROM. This ROM is reserved for firmware to support booting and extended core
functions, therefore it does not contain user programs.
Make sure this area is not accessed from the user program or debugger.
i.6.4area2(Debugarea)
Area 2 is a debugging-only area allocated for debugging resources. This area can only be accessed for writing in
debug mode.
Make sure this area is not accessed from the user program or debugger.
i.6.5area3(ivraM)
0x80000 to 0x82FFF in Area 3 is allocated to the 12K-byte IVRAM (Internal Video RAM) by the default
configuration. IVRAM can be used as a video RAM for the LCDC. The LCDC and CPU access IVRAM through
their respective 32-bit AHB bus and the IVRAM Arbiter that resolves bus conflicts between the LCDC and CPU.
IVRAM located in Area 3 can be accessed in a minimum of 2-wait cycles.
As described in Section I.6.2, IVRAM can be located in Area 0 for use as a high-speed general-purpose RAM that
allows no wait access when it is not used as a video RAM.
note: A program cannot be executed in the IVRAM located in Area 3.
i.6.6area3(DstraM)
0x84000 to 0x847FF in Area 3 is allocated to the 2K-byte DST RAM (Descriptor Table RAM). DST RAM is
provided for storing IDMA control words as A0RAM cannot contain them. The memory space other than control
words can be used as a general-purpose RAM and may also be specified as the source and destination of DMA
transfer.
DST RAM can be accessed in a minimum of 2-wait cycles.
note: The upper 256 bytes (0x84700 to 0x847FF) in DST RAM are reserved for use as the debugging
area. The user program must be prohibited from accessing this area.
However, specify 0x84780 for the debug RAM address of the c33 das command in the debugger.
c33 das 0x60000 0x84780 1
i.6.7area6(i/oarea)
Area 6 is allocated to the I/O area for S1C33L17 IP and peripheral circuits.
Although Area 6 is one of the external memory areas, external memory cannot be accessed.
For details of the internal peripheral circuits mapped to this area, see the description in Chapters III to IX. For
details of a control register list, see “I/O Map” in the Appendix.
i.6.8externalMemoryareas
Areas 4, 5, and 7 to 22 can be used for external memory and other external devices. Set up the SRAMC or
SDRAMC according to specifications of the devices connected.
Although the internal address and internal data buses of the S1C33L17 are both 32 bits wide, the maximum
external data bus width is 16 bits (D[15:0]) and the maximum external address bus width is 25 bits (A[24:0]) due to
the limited number of pins available.