
iiiPeriPheraLModuLes1(systeM):interruPtControLLer(itC)
s1C33L17teChniCaLManuaL
ePson
iii-2-1
III
ITC
III.2 Interrupt Controller (ITC)
The S1C33L17 contains an interrupt controller, making it possible to control all interrupts generated by the internal
peripheral circuits. This section explains the functions of this interrupt controller centering around the method for
controlling maskable interrupts. For details about the various causes and conditions under which interrupts are
generated, refer to the description of each peripheral circuit in this manual.
iii.2.1outlineofinterruptFunctions
iii.2.1.1Maskableinterrupts
The ITC can handle the following kind of maskable interrupts. Table III.2.1.1.1 shows the trap table in the
S1C33L17.
TableIII.2.1.1.1TrapTable
idMa
Ch.
–
1
2
3
4
–
5
6
–
7
8
–
9
10
–
11
12
–
13
14
–
Priority
1
–
4
3
–
2
5
6
–
High
↑
↓
Low
Vectornumber
(hexaddress)
0(Base)
1
2(Base+8)
3(Base+0C)
4–5
6(Base+18)
0x60000
7(Base+1C)
8–10
11(Base+2C)
12(Base+30)
13(Base+34)
14(Base+38)
15(Base+3C)
16(Base+40)
17(Base+44)
18(Base+48)
19(Base+4C)
20(Base+50)
21(Base+54)
22(Base+58)
23(Base+5C)
24(Base+60)
25(Base+64)
26(Base+68)
27–29
30(Base+78)
31(Base+7C)
32–33
34(Base+88)
35(Base+8C)
36–37
38(Base+98)
39(Base+9C)
40–41
42(Base+A8)
43(Base+AC)
44–55
exception/interruptname
(peripheralcircuit)
Reset
reserved
extexception
Undefinedinstructionexception
reserved
Addressmisalignedexception
Debuggingexception
NMI
reserved
Illegalinterruptexception
Softwareexception0
Softwareexception1
Softwareexception2
Softwareexception3
Portinputinterrupt0
Portinputinterrupt1
Portinputinterrupt2
Portinputinterrupt3
Keyinputinterrupt0
Keyinputinterrupt1
High-speedDMACh.0
High-speedDMACh.1
High-speedDMACh.2
High-speedDMACh.3
IntelligentDMA
reserved
16-bittimer0
reserved
16-bittimer1
reserved
16-bittimer2
reserved
16-bittimer3
reserved
Causeofexception/interrupt
Lowinputtotheresetpin
–
extinstruction(illegaluse)
Undefinedinstruction
–
Memoryaccessinstruction
brkinstruction,etc.
Lowinputtothe#NMIpin
orwatchdogtimeroverflow
–
OccurrenceofillegalinterruptfromITC
intinstruction
Edge(risingorfalling)orlevel(HighorLow)
Risingorfallingedge
High-speedDMACh.0,endoftransfer
High-speedDMACh.1,endoftransfer
High-speedDMACh.2,endoftransfer
High-speedDMACh.3,endoftransfer
IntelligentDMA,endoftransfer
–
Timer0compare-matchB
Timer0compare-matchA
–
Timer1compare-matchB
Timer1compare-matchA
–
Timer2compare-matchB
Timer2compare-matchA
–
Timer3compare-matchB
Timer3compare-matchA
–