
iiiPeriPheraLModuLes1(systeM):CLoCkManageMentunit(CMu)
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iii-1-17
III
CMU
iii.1.9ControllingClocksupply
To reduce power consumption on the chip, a function is provided to turn off clock supply independently for each
functional module.
iii.1.9.1MCLkClocksupplytoeachModule
Table III.1.9.1.1 lists the register bits used for on/off control of MCLK clock supply to the internal modules. The
modules listed here have one controllable clock path, so they can be turned on/off using the corresponding control
bit only. See Sections III.1.9.3 to III.1.9.9 for controlling the LCDC, SDRAMC, SRAMC, GPIO, EFSIO, USB, and
RTC clocks.
TableIII.1.9.1.1MCLKClockSupplyControlBits
Module
DSTRAM(Area3RAM)
16-bittimer3
16-bittimer2
16-bittimer1
16-bittimer0
ExtendedGPIO/
Miscregisters(0x300C41–0x300C4D)
I2S
Watchdogtimer
SPI
CARD
A/Dconverter
ITC
DMAC
Controlbit
DSTRAM_CKE
(D3)
TM3_CKE
(D16)
TM2_CKE
(D15)
TM1_CKE
(D14)
TM0_CKE
(D13)
EGPIO_MISC_CKE (D12)
I2S_CKE
(D11)
WDT_CKE
(D9)
SPI_CKE
(D6)
CARD_CKE
(D4)
ADC_CKE
(D3)
ITC_CKE
(D2)
DMA_CKE
(D1)
Controlregister
GatedClockControlRegister0(0x301B00)
GatedClockControlRegister1(0x301B04)
When initially reset, these control bits are set to 1 (on), with clocks supplied to each module. If any module is
unused, set the corresponding control bit to 0, thus turning the clock for that module off.
notes: TheseclocksdonotstopinHALTmode.TostopsupplyingtheclockinHALTmode,thecontrol
bitshouldbesetto0beforeexecutingthehaltinstruction.
AlltheseclocksstopinSLEEPmode.
The clock supply to any module can only be stopped when the module is not operating or
unused.Ifclocksupplytoanymoduleisstoppedwhenthemoduleisbeingoperatedorused,
thechipmayhang.
iii.1.9.2automaticClockControlinhaLtMode
The clocks for the functions listed in Table III.1.9.2.1 can be automatically stopped in HALT mode by setting the
control bits.
TableIII.1.9.2.1ClockSupplyControlBitstoDisableinHALTMode
Function
SDRAMCCPU_AHBbusI/F
CPU_AHBbuscontrol
LCDC_AHBbuscontrol
GPIOinput/interruptcontrol
SRAMC
EFSIObaudratetimer
Miscregisters(0x300010–0x300020)
Controlbit
SDAPCPU_HCKE (D7)
CPUAHB_HCKE (D29)
LCDCAHB_HCKE (D28)
GPIONSTP_HCKE (D27)
SRAMC_HCKE
(D26)
EFSIOBR_HCKE (D25)
MISC_HCKE
(D24)
Controlregister
GatedClockControlRegister0(0x301B00)
GatedClockControlRegister1(0x301B04)
When initially reset, these control bits are set to 1 (on) to enable clock supply in HALT mode. If any clock is
unused in HALT mode, set the corresponding control bit to 0 (off). The clock supply stops when the CPU enters
HALT mode.
note: AlltheseclocksstopinSLEEPmoderegardlesshowthesecontrolbitsareset.