
ViPeRiPheRaLMoDuLes4(PoRts):GeneRaL-PuRPosei/oPoRts(GPio)
Vi-1-10
ePson
s1C33L17teChniCaLManuaL
Vi.1.6DetailsofControlRegisters
TableVI.1.6.1ListofI/OPortRegisters
address
0x00300380
0x00300381
0x00300382
0x00300383
0x00300384
0x00300385
0x00300386
0x00300387
0x00300388
0x00300389
0x0030038A
0x0030038B
0x0030038C
0x0030038D
0x0030038E
0x00300390
0x00300391
0x00300392
0x00300393
0x003003A0
0x003003A1
0x003003A2
0x003003A3
0x003003A4
0x003003A5
0x003003A6
0x003003A7
0x003003A8
0x003003A9
0x003003AA
0x003003AB
0x003003AC
0x003003AD
0x003003AE
0x003003AF
0x003003B0
0x003003B1
0x003003B2
0x003003B3
0x003003C0
0x003003C1
0x003003C2
0x003003C3
0x003003C4
0x003003C5
0x003003C6
0x003003C7
0x003003D0
0x003003D2
0x003003D3
0x003003D4
0x003003D5
Function
P0portdataread/writeregister
ControlsP0portinput/outputdirection.
P1portdataread/writeregister
ControlsP1portinput/outputdirection.
P2portdataread/writeregister
ControlsP2portinput/outputdirection.
P3portdataread/writeregister
ControlsP3portinput/outputdirection.
P4portdataread/writeregister
ControlsP4portinput/outputdirection.
P5portdataread/writeregister
ControlsP5portinput/outputdirection.
P6portdataread/writeregister
ControlsP6portinput/outputdirection.
P7portdataread/writeregister
P8portdataread/writeregister
ControlsP8portinput/outputdirection.
P9portdataread/writeregister
ControlsP9portinput/outputdirection.
SetsP00–P03portpinfunction.
SetsP04–P07portpinfunction.
SetsP10–P13portpinfunction.
SetsP14–P17portpinfunction.
SetsP20–P23portpinfunction.
SetsP24–P27portpinfunction.
SetsP30–P33portpinfunction.
SetsP34–P36portpinfunction.
SetsP40–P43portpinfunction.
SetsP44–P47portpinfunction.
SetsP50–P53portpinfunction.
SetsP54–P57portpinfunction.
SetsP60–P63portpinfunction.
SetsP64–P67portpinfunction.
SetsP70–P73portpinfunction.
SetsP74portpinfunction.
SetsP80–P83portpinfunction.
SetsP84–P85portpinfunction.
SetsP90–P93portpinfunction.
SetsP94–P97portpinfunction.
SelectsportsusedforFPT0–FPT3portinput
interrupts.
SelectsportsusedforFPT4–FPT7portinput
interrupts.
SelectssignalpolaritytogenerateFPT0–FPT7port
inputinterrupts.
SelectsFPT0–FPT7portinterrupttriggercondition.
SelectsportsusedforFPT8–FPT11portinput
interrupts.
SelectsportsusedforFPT12–FPT15portinput
interrupts.
SelectssignalpolaritytogenerateFPT8–FPT15port
inputinterrupts.
SelectsFPT8–FPT15portinterrupttriggercondition.
Selectsportsusedforkeyinputinterrupts.
SetsFPK0interrupttriggeredgecondition.
SetsFPK1interrupttriggeredgecondition.
Enables/disablesportsforgeneratingFPK0
interrupts.
Enables/disablesportsforgeneratingFPK1
interrupts.
Registername
P0PortDataRegister(pP0_P0D)
P0I/OControlRegister(pP0_IOC0)
P1PortDataRegister(pP1_P1D)
P1I/OControlRegister(pP1_IOC1)
P2PortDataRegister(pP2_P2D)
P2I/OControlRegister(pP2_IOC2)
P3PortDataRegister(pP3_P3D)
P3I/OControlRegister(pP3_IOC3)
P4PortDataRegister(pP4_P4D)
P4I/OControlRegister(pP4_IOC4)
P5PortDataRegister(pP5_P5D)
P5I/OControlRegister(pP5_IOC5)
P6PortDataRegister(pP6_P6D)
P6I/OControlRegister(pP6_IOC6)
P7PortDataRegister(pP7_P7D)
P8PortDataRegister(pP8_P8D)
P8I/OControlRegister(pP8_IOC8)
P9PortDataRegister(pP9_P9D)
P9I/OControlRegister(pP9_IOC9)
P00–P03PortFunctionSelectRegister(pP0_03_CFP)
P04–P07PortFunctionSelectRegister(pP0_47_CFP)
P10–P13PortFunctionSelectRegister(pP1_03_CFP)
P14–P17PortFunctionSelectRegister(pP1_47_CFP)
P20–P23PortFunctionSelectRegister(pP2_03_CFP)
P24–P27PortFunctionSelectRegister(pP2_47_CFP)
P30–P33PortFunctionSelectRegister(pP3_03_CFP)
P34–P36PortFunctionSelectRegister(pP3_46_CFP)
P40–P43PortFunctionSelectRegister(pP4_03_CFP)
P44–P47PortFunctionSelectRegister(pP4_47_CFP)
P50–P53PortFunctionSelectRegister(pP5_03_CFP)
P54–P57PortFunctionSelectRegister(pP5_47_CFP)
P60–P63PortFunctionSelectRegister(pP6_03_CFP)
P64–P67PortFunctionSelectRegister(pP6_47_CFP)
P70–P73PortFunctionSelectRegister(pP7_03_CFP)
P74PortFunctionSelectRegister(pP7_4_CFP)
P80–P83PortFunctionSelectRegister(pP8_03_CFP)
P84–P85PortFunctionSelectRegister(pP8_45_CFP)
P90–P93PortFunctionSelectRegister(pP9_03_CFP)
P94–P97PortFunctionSelectRegister(pP9_47_CFP)
PortInputInterruptSelectRegister1
(pPINTSEL_SPT03)
PortInputInterruptSelectRegister2
(pPINTSEL_SPT47)
PortInputInterruptPolaritySelectRegister1
(pPINTPOL_SPP07)
PortInputInterruptEdge/LevelSelectRegister1
(pPINTEL_SEPT07)
PortInputInterruptSelectRegister3
(pPINTSEL_SPT811)
PortInputInterruptSelectRegister4
(pPINTSEL_SPT1215)
PortInputInterruptPolaritySelectRegister2
(pPINTPOL_SPP815)
PortInputInterruptEdge/LevelSelectRegister2
(pPINTEL_SEPT815)
KeyInputInterruptSelectRegister(pKINTSEL_SPPK01)
KeyInputInterrupt(FPK0)InputComparisonRegister
(pKINTCOMP_SCPK0)
KeyInputInterrupt(FPK1)InputComparisonRegister
(pKINTCOMP_SCPK1)
KeyInputInterrupt(FPK0)InputMaskRegister
(pKINTCOMP_SMPK0)
KeyInputInterrupt(FPK1)InputMaskRegister
(pKINTCOMP_SMPK1)
size
8
The following describes each I/O port control register. The I/O port control registers are mapped in the 8-bit device
area from 0x300380 to 0x3003D5, and can be accessed in units of bytes.