
aPPendix a i/o MaP
s1C33L17 teChniCaL ManuaL
ePson
aP-a-43
AP
I/Omap
0x30098a–0x300999
usB Function Controller
name
address
Register name
Bit
setting
init. R/W
Remarks
D7–2
D1
D0
–
0
–
R/W
0 when being read.
0030098a
(B)
descsize_h
(descriptor
size high)
–
Descriptor size
–
descsize[9]
descsize[8]
descsize[7]
descsize[6]
descsize[5]
descsize[4]
descsize[3]
descsize[2]
descsize[1]
descsize[0]
D7
D6
D5
D4
D3
D2
D1
D0
0
R/W
0030098B
(B)
descsize_L
(descriptor
size low)
Descriptor size
descMode[7]
descMode[6]
descMode[5]
descMode[4]
descMode[3]
descMode[2]
descMode[1]
descMode[0]
D7
D6
D5
D4
D3
D2
D1
D0
0
R/W
0030098F
(B)
descdoor
(descriptor
door)
Descriptor door
D7
D6
D5–0
0 when being read.
00300990
(B)
dMa_FiFo_Control
(dMa FiFo
control)
0
–
R
R/W
–
1 FIFO is running
0 FIFO is not running
1 Auto enable short packet
0 Do nothing
FiFo_Running
autoenshort
–
JoinePddMa
JoinePcdMa
JoinePbdMa
JoinePadMa
D7–4
D3
D2
D1
D0
–
0
–
R/W
0 when being read.
00300991
(B)
–
1 Join EPc to DMA
0 Do nothing
1 Join EPb to DMA
0 Do nothing
1 Join EPa to DMA
0 Do nothing
dMa_Join
(dMa join
FiFo)
1 Join EPd to DMA
0 Do nothing
D7
D6
D5
D4
D3
D2
D1
D0
0 when being read.
00300992
(B)
dMa_Control
(dMa control)
0
–
0
–
0
R
–
W
–
W
–
PDACK signal logic
PDREQ signal logic
–
1 DMA is running
0 DMA is not running
1 Clear DMA counter
0 Do nothing
1 Finish DMA
0 Do nothing
1 Start DMA
0 Do nothing
dMa_Running
PdReQ
PdaCK
–
CounterClr
–
dMa_stop
dMa_Go
D7
D6–4
D3
D2
D1
D0
0 when being read.
00300994
(B)
dMa_Config_0
(dMa
configuration 0)
0
–
0
–
R/W
–
R/W
–
1 Activate DMA port
0 Disactivate DMA port
1 Active-low
0 Active-high
1 Active-low
0 Active-high
1 Active-low
0 Active-high
activePort
–
PdReQ_Level
PdaCK_Level
PdRdWR_Level
–
D7
D6–4
D3
D2–1
D0
0
–
0
–
0
R/W
–
R/W
–
R/W
0 when being read.
00300995
(B)
dMa_Config_1
(dMa
configuration 1)
RcvLimitMode
–
singleWord
–
CountMode
–
1 Receive limit mode
0 Normal
1 Single word
0 Multi word
1 Count-down mode
0 Free-run mode
D7–4
D3
D2
D1
D0
–
0
–
R/W
0 when being read.
00300997
(B)
dMa_Latency
(dMa latency)
–
Latency
–
dMa_Latency[3]
dMa_Latency[2]
dMa_Latency[1]
dMa_Latency[0]
–
dMa_Remain[11]
dMa_Remain[10]
dMa_Remain[9]
dMa_Remain[8]
D7–4
D3
D2
D1
D0
–
0
–
R
0 when being read.
00300998
(B)
dMa_Remain_h
(dMa FiFo
remain high)
DMA FIFO remain high
–
dMa_Remain[7]
dMa_Remain[6]
dMa_Remain[5]
dMa_Remain[4]
dMa_Remain[3]
dMa_Remain[2]
dMa_Remain[1]
dMa_Remain[0]
D7
D6
D5
D4
D3
D2
D1
D0
0
R
00300999
(B)
dMa_Remain_L
(dMa FiFo
remain low)
DMA FIFO remain low