
iiBusModuLes:high-sPeeddMa(hsdMa)
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ii-1-29
II
HSDMA
0x301122–0x301152:hsdMaCh.xControlRegisters
name
address
Registername
Bit
Function
setting
init. R/W
Remarks
–
duaLMx
dxdiR
–
tCx_h7
tCx_h6
tCx_h5
tCx_h4
tCx_h3
tCx_h2
tCx_h1
tCx_h0
D15
D14
D13–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.xaddressmodeselection
D)Invalid
S)Ch.xtransferdirectioncontrol
reserved
Ch.xtransfercounter[15:8]
(blocktransfermode)
Ch.xtransfercounter[23:16]
(single/successivetransfermode)
1 Dualaddr
0 Singleaddr
1 MemoryWR 0 MemoryRD
0
–
0
–
0
R/W
–
R/W
–
R/W
0whenbeingread.
00301122
|
00301152
(hW)
hsdMaCh.x
controlregister
Note:
D) Dualaddress
mode
S) Single
address
mode
note: Theletter‘x’inbitnames,etc.,denotesachannelnumberfrom0to3.
0x301122 HSDMACh.0ControlRegister
0x301132 HSDMACh.1ControlRegister
0x301142 HSDMACh.2ControlRegister
0x301152 HSDMACh.3ControlRegister
d15
duaLMx:Ch.xaddressModeselectBit
Select an address mode.
1 (R/W): Dual-address mode
0 (R/W): Single-address mode (default)
When 1 is written to DUALMx, the HSDMA channel enters dual-address mode that allows specifica-
tion of source and destination addresses. When 0 is written, the HSDMA channel enters single-address
mode for high-speed data transfer between the external memory and an I/O device.
d14
dxdiR:Ch.xtransferdirectionControlBit
Control the direction of data transfer in single-address mode.
1 (R/W): Memory write
0 (R/W): Memory read (default)
Data transfer from an external I/O device to external memory (or an external/internal I/O) is performed
by writing 1 to DxDIR. Data transfer from external memory (or an external/internal I/O) to an external
I/O is performed by writing 0.
This bit is effective only in single-address mode.
d[13:8] Reserved
d[7:0]
tCx_h[7:0]:Ch.xtransferCounterBits
Set the data transfer count. (Default: 0x00)
In block transfer mode, TCx_H[7:0] is bits[15:8] of the transfer counter. In single or successive transfer
mode, TCx_H[7:0] is bits[23:16] of the transfer counter.
This counter is decremented each time a DMA transfer in the corresponding channel is performed.
When the counter reaches 0, a cause of interrupt is generated. In single-address mode, the end-of-trans-
fer signal is output from the #DMAENDx pin at the same time. Even when the counter is 0, a DMA
request is accepted and the counter is decremented to 0xFFFF (or 0xFFFFFF).
Be sure to disable DMA transfers (HSx_EN (D0/0x30112C + 0x10x) = 0) before writing and reading
to and from the counter.