
iiBusModuLes:high-sPeeddMa(hsdMa)
ii-1-42
ePson
s1C33L17teChniCaLManuaL
0x301168–0x30119a:hsdMaCh.xdestinationaddresssetupRegisters
(phsx_adV_dadR)foradVmode
name
address
Registername
Bit
Function
setting
init. R/W
Remarks
dxadRL15
dxadRL14
dxadRL13
dxadRL12
dxadRL11
dxadRL10
dxadRL9
dxadRL8
dxadRL7
dxadRL6
dxadRL5
dxadRL4
dxadRL3
dxadRL2
dxadRL1
dxadRL0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D)Ch.xdestinationaddress[15:0]
S)Invalid
0
R/W
00301168
|
00301198
(hW)
hsdMaCh.x
low-order
destination
addresssetup
register
(pHSx_ADV_DADR)
forADVmode
Note:
D) Dualaddress
mode
S) Single
address
mode
dxadRh15
dxadRh14
dxadRh13
dxadRh12
dxadRh11
dxadRh10
dxadRh9
dxadRh8
dxadRh7
dxadRh6
dxadRh5
dxadRh4
dxadRh3
dxadRh2
dxadRh1
dxadRh0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D)Ch.xdestinationaddress[31:16]
S)Invalid
0
R/W
0030116a
|
0030119a
(hW)
hsdMaCh.x
high-order
destination
addresssetup
register
forADVmode
Note:
D) Dualaddress
mode
S) Single
address
mode
notes: Thisregisteriseffectiveonlyinadvancedmode(HSDMAADV(D0/0x30119C)=1).
Theletter‘x’inbitnames,etc.,denotesachannelnumberfrom0to3.
0x301168 HSDMACh.0Low-OrderDestinationAddressSetupRegister(pHS0_ADV_DADR)
0x30116A HSDMACh.0High-OrderDestinationAddressSetupRegisterforADVmode
0x301178 HSDMACh.1Low-OrderDestinationAddressSetupRegister(pHS1_ADV_DADR)
0x30117A HSDMACh.1High-OrderDestinationAddressSetupRegisterforADVmode
0x301188 HSDMACh.2Low-OrderDestinationAddressSetupRegister(pHS2_ADV_DADR)
0x30118A HSDMACh.2High-OrderDestinationAddressSetupRegisterforADVmode
0x301198 HSDMACh.3Low-OrderDestinationAddressSetupRegister(pHS3_ADV_DADR)
0x30119A HSDMACh.3High-OrderDestinationAddressSetupRegisterforADVmode
d[15:0]/0x301168–0x301198
dxadRL[15:0]:Ch.xdestinationaddress[15:0]
d[15:0]/0x30116a–0x30119a
dxadRh[15:0]:Ch.xdestinationaddress[31:16]
In dual-address mode, these bits are used to specify a 32-bit destination address.
Be sure to disable DMA transfers (HSx_EN (D0/0x30112C + 0x10x) = 0) before writing or reading to
and from these registers.
The address is incremented or decremented (as set by DxIN[1:0] (D[13:12]/0x30112A + 0x10x) or
DxID (D5/0x301162 + 0x10x)) according to the transfer data size each time a DMA transfer in the cor-
responding channel is performed.