
is1C33L17sPeCifiCations:overview
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efsio(extendedserialinterfacewithfifoBuffer)
2-ch. clock sync./async. serial interface
Contains FIFO data buffers (4 receive data buffer and 2 transmit data buffer are available for each
channel).
Supports IrDA1.0 interface.
Contains a baud-rate generator (12-bit programmable timer).
Supports ISO7816 mode (Ch.1 only).
- Alternative MSB or LSB
- Memory card interface compatible with ISO7816-3 T=0 & T=1 protocol
- Programmable baud-rate and guard-time generation
- ISO7816 acknowledge and automatically repeat transmission
Possible to invoke DMA transfer.
uart
Async. only Serial Interface (UART) with 1 byte Transmit data buffer and 2 bytes Receive data buffer
(Ch.2).
Built-in programmable 12-bit timer is available for baud-rate generators.
Possible to invoke DMA Transfer.
sPi(serialPeripheralinterface)
1 ch. SPI that operates in either master or slave mode
Supports 1- to 32-bit data transfer.
Data transfer timing (clock phase and polarity variations) is selectable from among 4 types.
A 1 to 65,536 clocks of delay can be inserted between transfers.
Generates transmit data register empty and receive data register full interrupts.
Support both MMC & SD Card capabilities.
Possible to invoke DMA transfer.
Max. Bit Rate in Master mode is MCLK/2.
egPio(extendedgPio)
Max. 17 configurable GPIO ports are available in addition to the standard GPIO ports. In die form, Max.
91 ports are available.
* The EGPIO ports are shared with other peripheral function pins. Therefore, the number of EGPIO
ports depends on the peripheral functions used.
Most ports have a pull-up resistor that can be enabled/disabled with the control register.
Possible to drive the ports low.
CMu(extendedClockManagementunit)
Controls clock supply to each peripheral module (static).
Manages reset and NMI inputs.
Switches the system clock source (MCLK, SDRAM_CLK, or RTC_CLK).
Controls the MCLK and RTC_CLK oscillator circuits.
Turns on/off and controls frequency multiplication rate of the PLL.
Controls clocks according to the standby mode (SLEEP and HALT).
Controls divide ratios of the LCDC clock.
Manages the external bus clock.
MisC(Misc.settingregister)
USB/RTC wait configuration registers
Debug port function select register
Boot mode configuration register