
ViPeRiPheRaLMoDuLes4(PoRts):GeneRaL-PuRPosei/oPoRts(GPio)
Vi-1-22
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Vi.1.7Precautions
After an initial reset, the cause-of-interrupt flags become indeterminate. To prevent generation of an unwanted
interrupt or IDMA request, be sure to reset the flags in a program.
To prevent regeneration of interrupts due to the same cause of interrupt following the occurrence of an interrupt,
always be sure to reset the cause-of-interrupt flag before resetting the PSR or executing the reti instruction.
When using an port input interrupt as the trigger to restart from the SLEEP mode, an interrupt will occur due to
the input signal level even if edge interrupt is specified as an interrupt condition. The signal level to restart the
CPU is as follows according to the signal edge selected:
If a rising-edge interrupt is set, the CPU restarts when the input signal goes to a high level.
If a falling-edge interrupt is set, the CPU restarts when the input signal goes to a low level.
When a falling edge interrupt is selected to restart after the slp instruction is executed, the operation is as follows.
If the interrupt port is already at a low level when the slp instruction is executed, the CPU enters SLEEP mode
instantaneously and restarts immediately afterward.
If the interrupt port is at a high level when the slp instruction is executed, the SLEEP mode continues until the
port goes low.
Therefore, design the system assuming that the CPU can restart normally due to the signal level at the interrupt
port, not an edge interrupt, when restarting the CPU from SLEEP mode using a port input interrupt.
To use the P15–P17 and P34–P36 pins that are configured as the debug interface pins by default for general-
purpose inputs/outputs, clear TRCMUX (D0/0x300014) to 0.
*tRCMuX:P15–17,P34–36DebugFunctionSelectBitintheDebugPortMUXRegister(D0/0x300014)
Note, however, that the PC trace function of the debugger cannot be used when TRCMUX (D0/0x300014) is set
to 0.
Even if the port input interrupt condition is set to falling edge, the input pulse width must be longer than 1 cycle
of the port operating clock (= MCLK) to be certain an interrupt will be generated.