
iiiPeriPheraLModuLes1(systeM):CLoCkManageMentunit(CMu)
s1C33L17teChniCaLManuaL
ePson
iii-1-1
III
CMU
III.1 Clock Management Unit (CMU)
iii.1.1overviewoftheCMu
The Clock Management Unit (CMU) controls the operating clock supplied to each functional module. The main
functions of the CMU are outlined below.
Controls reset and NMI inputs
Selects the system clock source (OSC3, PLL, or OSC1)
Controls on/off of the OSC3 and OSC1 oscillator circuits
Controls on/off and frequency multiplication rate of the PLL
Controls SSCG
Clock control corresponding to standby modes (SLEEP and HALT)
Selects divide ratio of the main system clock
Selects an external bus clock
Controls on/off of clock supply for each functional module
Through system clock selection, oscillator circuit, and PLL control, and main system clock divide ratio selection
and clock on/off control for each functional module, the CMU enables the most suitable operating clock frequency
to be selected for the processing involved, as well as to turn off unnecessary clock supply, which combined with
standby mode, helps to significantly reduce power consumption on the chip.
OSC/PLL/
SSCG
control
OSC3
oscillator
(48MHz)
Divider
(1/1–1/32)
Divider
(1/1–1/10)
OSC1
oscillator
(32.768kHz)
Reset/NMI
control
PLL
x1–x16
(20–90MHz)
Clock
switch
NMI
RESET
CMu
#NMI
#RESET
MCLKI
MCLKO
OSC3
PLLIN_DIV
OSC
OSCSEL
MCLKDIV
CMU_CLKSEL
11clocks
SLEEP
Wakeup,etc.
HALT
OSC_W
OSC3_DIV
PLL
OSC1
MCLK
ClockOn/Off
control
Toperipheral
modules
ClockOn/Off
controlin
HALTmode
Powerdown
control
ToAHBbusand
someperipheral
modules
ClockOn/Off
control
ToSDRAMC
ToC33PECore
ClockOn/Off
control
ToLCDC
CMU_CLK
ClockOn/Off
control
ToUSB
ToRTC
RTC_CLKI
RTC_CLKO
Divider
(1/1–1/16)
1/2
SSCG
FigureIII.1.1.1CMUBlockDiagram
note: The CMU Control Registers at addresses 0x301B00–0x301B14 are write-protected. Before the
CMUcontrolregisterscanberewritten,writeprotectionoftheseregistersmustberemovedby
writingdata0x96totheClockControlProtectRegister(0x301B24).Notethatsinceunnecessary
rewrites to addresses 0x301B00–0x301B14 could lead to erratic system operation, the Clock
ControlProtectRegister(0x301B24)shouldbesettootherthan0x96unlesssaidCMUcontrol
registersmustberewritten.