
iiBusModuLes:sdRaMContRoLLeR(sdRaMC)
s1C33L17teChniCaLManuaL
ePson
ii-4-11
II
SDRAMC
To execute the MRS/EMRS (Mode Register Set/Extended Mode Register Set) command:
Write 0x14 to the SDRAM Initial Register (0x301600); INIMRS (D2/0x301600) should be set to 1.
Then write any data to the specific address shown below according to the CAS latency (MRS) or
extended mode parameters (EMRS).
iniMRs:MRSCommandEnableforInitializationBitintheSDRAMInitialRegister(D2/0x301600)
TableII.4.1.5.1DataWriteAddresstoExecutetheMRS/EMRSCommand
CPuaddress
sdRaMaddress
MRs
CASlatency=1
CASlatency=2
CASlatency=3
eMRs
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
1
0
SeeSDRAMspecifications.
0
1
0
1
0
1
0
1
BA1
Mode
reserved
Testmode
CASlatency
WB
Burstlength
BT
Mode
reserved
DS
PASR
TCSR
BA0
SDA12 SDA11 SDA10 SDA9
SDA8
SDA7
SDA6
SDA5
SDA4
SDA3
SDA2
SDA1
SDA0
For example, to execute an MRS command with 2 of CAS latency specified, write data (any value) to
address 0x10000442 (when the SDRAM is mapped to area 19) after writing 0x14 to the SDRAM Initial
Register (0x301600).
notes: TheCASlatencyspecifiedintheMRScommandmustbethesameastheCAS[1:0](D[3:2]/
0x301610)setvalue.
Cas[1:0]: CASLatencySetupBitsintheSDRAMApplicationConfigurationRegister(D[3:2]/0x301610)
Aftertheinitialsequencecommandsareexecuted,thecommandenablebitsmustbesetto0.
Write0x10totheSDRAMInitialRegister(0x301600)afterthelastinitializationcommandhas
beenexecuted.
Theself-refreshfunctionmustbedisableduntiltheSDRAMhasfinishedinitialization.
5. Checking if the SDRAM has been initialized
SDEN (D3/0x301600) is reset to 0 after power-on, and is set to 1 upon completion of the initialization
sequence shown above. Make sure that SDEN (D3/0x301600) is set to 1 before the SDRAM is accessed.
In addition to being reset at power-on, SDEN (D3/0x301600) is reset to 0 by writing 0 to SDON (D4/
0x301600).
sden:SDRAMInitializeFlagintheSDRAMInitialRegister(D3/0x301600)
sdon:SDRAMControllerEnableBitintheSDRAMInitialRegister(D4/0x301600)
SDRAMpower
SDCLK
Command
SDCKE
#SDCS
#SDRAS
#SDCAS
#SDWE
DQMH/DQML
SDONbit
INIPREbit
INIREFbit
INIMRSbit
SDENbit
SDA10
SDBA[1:0]
SDA[12:11,9:0]
PALL NOP
NOP
H
REF
MRS
CMD
Valid
100
smin.
tRP
tRFC
VCC(Min.)
NOP
FigureII.4.1.5.1SDRAMPower-upandInitialization