
ViiiPeRiPheRaLMoDuLes6(LCD):LCDContRoLLeR(LCDC)
s1C33L17teChniCaLManuaL
ePson
Viii-1-35
VIII
LCDC
Viii.1.9DetailsofControlRegisters
TableVIII.1.9.1ListofLCDCRegisters
address
0x00301A00
0x00301A04
0x00301A10
0x00301A14
0x00301A18
0x00301A20
0x00301A24
0x00301A28
0x00301A2C
0x00301A30
0x00301A40
0x00301A44
0x00301A48
0x00301A4C
0x00301A60
0x00301A64
0x00301A70
0x00301A74
0x00301A80
0x00301A88
0x00301A8C
0x00301AA0
0x00301AA4
0x00301AA8
0x00301AAC
Function
EnablesLCDCinterrupts.
Controlspower-savemodeandindicatesinterrupt
status.
Setshorizontaltotalanddisplayperiods.
Setsverticaltotalanddisplayperiods.
SetsMODrate.
Setshorizontaldisplayperiodstartpositionfor
HR-TFT.
Setsverticaldisplayperiodstartpositionfor
HR-TFT.
SetsFPLINEpulseforHR-TFT.
SetsFPFRAMEpulseforHR-TFT.
SetsFPFRAMEpulseoffsetforHR-TFT.
ControlsHR-TFTsignals.
SetsTFT_CTL1pulse.
SetsTFT_CTL0pulse.
SetsTFT_CTL2signal.
Setsdisplaymodeandcontrolsdisplay.
SelectsIRAMallocation.
Setsmainwindowdisplaystartaddress.
Setsmainwindowlineaddressoffset.
Setssub-windowdisplaystartaddress.
Setssub-windowstartposition.
Setssub-windowendposition.
Look-uptabledata(entries0to3)
Look-uptabledata(entries4to7)
Look-uptabledata(entries8to11)
Look-uptabledata(entries12to15)
Registername
FrameInterruptRegister(pLCDC_INT)
StatusandPowerSaveConfigurationRegister(pLCDC_PS)
HorizontalDisplayRegister(pLCDC_HD)
VerticalDisplayRegister(pLCDC_VD)
MODRateRegister(pLCDC_MR)
HorizontalDisplayStartPositionRegister(pLCDC_HDPS)
VerticalDisplayStartPositionRegister(pLCDC_VDPS)
FPLINEPulseSetupRegister(pLCDC_L)
FPFRAMEPulseSetupRegister(pLCDC_F)
FPFRAMEPulseOffsetRegister(pLCDC_FO)
HR-TFTSpecialOutputRegister(pLCDC_TSO)
TFT_CTL1PulseRegister(pLCDC_TC1)
TFT_CTL0PulseRegister(pLCDC_TC0)
TFT_CTL2Register(pLCDC_TC2)
LCDCDisplayModeRegister(pLCDC_DMD)
IRAMSelectRegister(pLCDC_IRAM)
MainWindowDisplayStartAddressRegister(pLCDC_MADD)
MainWindowLineAddressOffsetRegister(pLCDC_MLADD)
Sub-windowDisplayStartAddressRegister(pLCDC_SADD)
Sub-windowStartPositionRegister(pLCDC_SSP)
Sub-windowEndPositionRegister(pLCDC_SEP)
Look-upTableDataRegister0(pLCDC_LUT_03)
Look-upTableDataRegister1(pLCDC_LUT_47)
Look-upTableDataRegister2(pLCDC_LUT_8B)
Look-upTableDataRegister3(pLCDC_LUT_CF)
size
32
The following describes each LCDC control register.
The LCDC control registers are mapped in the 32-bit device area from 0x301A00 to 0x301AAC, and can be ac-
cessed only in units of words.
note: WhensettingtheLCDCcontrolregisters,besuretowritea0,andnota1,forall“reservedbits.”