
is1C33L17sPeCifiCations:PinDesCriPtion
i-3-6
ePson
s1C33L17teChniCaLManuaL
i/o
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i
(Hi-Z)
i
(Hi-Z)
i
(Hi-Z)
i
(Hi-Z)
i
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
i/o
(Hi-Z)
Pull-
up/down
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
function
P32:
General-purpose I/O port (default)
CARD4:
Card I/F signal 4 output
#DMAREQ2: HSDMA Ch.2 request input
FPDAT14:
LCD Data
P33:
General-purpose I/O port (default)
CARD5:
Card I/F signal 5 output
#DMAREQ3: HSDMA Ch.3 request input
FPDAT15:
LCD Data
P60:
General-purpose I/O port (default)
SIN2:
Serial I/F Ch.2 data input
FPDAT15:
LCD Data
EXCL0:
16-bit timer 0 event counter input
P61:
General-purpose I/O port (default)
SOUT2:
Serial I/F Ch.2 data output
FPDAT14:
LCD Data
EXCL1:
16-bit timer 1 event counter input
P62:
General-purpose I/O port (default)
FPDAT12:
LCD Data
#ADTRG:
A/D converter trigger input
CMU_CLK: CMU external clock output
P63:
General-purpose I/O port (default)
FPDAT13:
LCD Data
WDT_CLK: Watchdog timer clock output
#WDT_NMI: Watchdog timer NMI signal output
P64:
General-purpose I/O port (default)
#WAIT:
Wait cycle request input
EXCL2:
16-bit timer 2 event counter input
P65:
General-purpose I/O port (default)
SDI:
SPI data input
FPDAT8:
LCD data
P66:
General-purpose I/O port (default)
SDO:
SPI data output
FPDAT9:
LCD data
P67:
General-purpose I/O port (default)
SPI_CLK:
SPI clock
FPDAT10:
LCD data
P70:
General-purpose I/O port (default)
AIN0:
A/D converter Ch.0 input
P71:
General-purpose I/O port (default)
AIN1:
A/D converter Ch.1 input
P72:
General-purpose I/O port (default)
AIN2:
A/D converter Ch.2 input
P73:
General-purpose I/O port (default)
AIN3:
A/D converter Ch.3 input
I2S_MCLK_EXT: External Input I2S Master Clock
P74:
General-purpose I/O port (default)
AIN4:
A/D converter Ch.4 input
EXCL3:
16-bit timer3 event counter input
P80:
General-purpose I/O port (default)
FPFRAME: LCD frame clock output
P81:
General-purpose I/O port (default)
FPLINE:
LCD line clock output
P82:
General-purpose I/O port (default)
FPSHIFT:
LCD shift clock output
P83:
General-purpose I/O port (default)
FPDRDY:
LCD DRDY/MOD signal output
TFT_CTL1: LCDC TFT I/F control signal 1 output
BCLK:
Bus clock output
P84:
General-purpose I/O port (default)
TM0:
16-bit Timer0 output
FPDAT11:
LCD data
P85:
General-purpose I/O port (default)
TM1:
16-bit Timer1 output
P90:
General-purpose I/O port (default)
FPDAT0:
LCD data
SDI:
SPI Data Input
P91:
General-purpose I/O port (default)
FPDAT1:
LCD data
SDO:
SPI Data Output
QfP
10
11
77
78
79
80
34
35
36
37
52
51
50
49
48
53
54
55
56
57
58
63
64
Pinno.
Pinname
P32
CARD4
#DMAREQ2
FPDAT14
P33
CARD5
#DMAREQ3
FPDAT15
P60
SIN2
FPDAT15
EXCL0
P61
SOUT2
FPDAT14
EXCL1
P62
FPDAT12
#ADTRG
CMU_CLK
P63
FPDAT13
WDT_CLK
#WDT_NMI
P64
#WAIT
EXCL2
P65
SDI
FPDAT8
P66
SDO
FPDAT9
P67
SPI_CLK
FPDAT10
P70
AIN0
P71
AIN1
P72
AIN2
P73
AIN3
I2S_MCLK_EXT
P74
AIN4
EXCL3
P80
FPFRAME
P81
FPLINE
P82
FPSHIFT
P83
FPDRDY
TFT_CTL1
BCLK
P84
TM0
FPDAT11
P85
TM1
P90
FPDAT0
SDI
P91
FPDAT1
SDO
PfBga
E4
E1
L13
K12
J12
K14
K3
M2
M3
N1
N6
M6
N7
M5
N5
P7
L6
L7
M7
L8
M8
L10
L11