
is1C33L17sPeCifiCations:PinDesCriPtion
i-3-4
ePson
s1C33L17teChniCaLManuaL
i/o
i/
o
(H)
i/
o
(H)
i/
o
( L)
o
3
i/
o
(H)
i/
o
(H)
i/o
(PU)
i/
o
(H)
i/
o
(H)
i/
o
(H)
i/
o
(H)
i/o
(PU)
i/o
(PU)
i/o
(PU)
i/o
(PU)
i/o
(PU)
i/o
(PU)
i/o
(PU)
i/o
(PU)
Pull-
up/down
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
function
A22:
Address bus (A22) (default)
P42:
General-purpose I/O port
FPDAT8:
LCD data
A23:
Address bus (A23) (default)
P41:
General-purpose I/O port
FPDAT13: LCD Data
#SDRAS: SDRAM row address strobe signal
A24:
Address bus (A24) (default)
P40:
General-purpose I/O port
FPDAT12: LCD Data
#SDCAS: SDRAM column address strobe signal output
Read signal
Write (low byte) signal
Write (high byte) signal or bus strobe (high byte) signal
#CE10:
Chip enable signal for areas 10, 13 and 20 (default)
P57:
General-purpose I/O port
#CE4:
Chip enable signal for areas 4 and 14 (default)
P50:
General-purpose I/O port
CARD0:
Card I/F signal 0 output
#CE5:
Chip enable signal for areas 5, 15 and 16 (default)
P51:
General-purpose I/O port
CARD1:
Card I/F signal 1 output
P52:
General-purpose I/O port (default)
BCLK:
Bus clock output
#CE6:
Chip enable signal for areas 6, 17 and 18
CMU_CLK: CMU external clock output
#CE7:
Chip enable signal for areas 7 and 19 (default)
P53:
General-purpose I/O port
SDA10:
SDRAM address bit 10
#CE8:
Chip enable signal for areas 8 and 21 (default)
P54:
General-purpose I/O port
CARD1:
Card I/F signal 1 output
FPDAT15: LCD Data
#CE9:
Chip enable signal for areas 9 and 22 (default)
P55:
General-purpose I/O port
CARD0:
Card I/F signal 0 output
FPDAT14: LCD Data
#CE11:
Chip enable signal for areas 11 and 12 (default)
P56:
General-purpose I/O port
P20:
General-purpose I/O port (default)
SDCKE:
SDRAM clock enable signal output
SDCLK:
SDRAM clock output (default)
P21:
General-purpose I/O port
P22:
General-purpose I/O port (default)
#SDCS:
SDRAM chip enable signal output
P23:
General-purpose I/O port (default)
#SDRAS: SDRAM row address strobe signal output
TFT_CTL1: LCDC TFT I/F control signal 1 output
P24:
General-purpose I/O port (default)
#SDCAS: SDRAM column address strobe signal output
P25:
General-purpose I/O port (default)
#SDWE:
SDRAM write signal output
P26:
General-purpose I/O port (default)
DQML:
SDRAM data (low byte) input/output mask signal output
P27:
General-purpose I/O port (default)
DQMH:
SDRAM data (high byte) input/output mask signal output
QfP
6
133
134
137
138
139
136
142
143
141
115
144
1
140
102
103
104
106
107
108
109
110
Pinno.
Pinname
a22
P42
FPDAT8
a23
P41
FPDAT13
#SDRAS
a24
P40
FPDAT12
#SDCAS
#rD
#wrL
#wrh/
#Bsh
#Ce10
P57
#Ce4
P50
CARD0
#Ce5
P51
CARD1
P52
BCLK
#CE6
CMU_CLK
#Ce7
P53
SDA10
#Ce8
P54
CARD1
FPDAT15
#Ce9
P55
CARD0
FPDAT14
#Ce11
P56
P20
SDCKE
sDCLk
P21
P22
#SDCS
P23
#SDRAS
TFT_CTL1
P24
#SDCAS
P25
#SDWE
P26
DQML
P27
DQMH
PfBga
C1
A6
C6
A5
C5
B4
B5
A3
B3
C4
A10
A2
B2
A4
D13
D14
C14
C13
B14
B13
A13
B12