
aPPendix a i/o MaP
s1C33L17 teChniCaL ManuaL
ePson
aP-a-85
AP
I/Omap
0x301C00–0x301C20
i2s interface
Register name
address
Bit
name
Function
setting
init. R/W
Remarks
i2s start/stop
Register
(pi2s_staRt)
0x00301C10
(32 bits)
D31–9 –
reserved
–
0 when being read.
D8
i2sstaRt1 I2S CH.1 start/stop control
1 Start
0 Stop
0
R/W
D7
i2sBusY0 I2S CH.0 busy flag
1 Busy
0 Idle
0
R
D6–1 –
reserved
–
0 when being read.
D0
i2sstaRt0 I2S CH.0 start/stop control
1 Start (run)
0 Stop
0
R/W
i2s FiFo status
Register
(pi2s_FiFo_
status)
0x00301C14
(32 bits)
D31–10 –
reserved
–
0 when being read.
D9
i2sFiFoFF1 I2S CH.1 FIFO full flag
1 Full
0 Not full
0
R
D8
i2sFiFoeF1 I2S CH.1 FIFO empty flag
1 Empty
0 Not empty
1
R
D7–5 –
reserved
–
0 when being read.
D4–2 FiFostat0
[2:0]
I2S CH.0 FIFO state machine FIFOSTAT0[2:0]
State
0x0
R
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
FLUSH
EMPTY
LACK
FULL
INIT
STOP
D1
i2sFiFoFF0 I2S CH.0 FIFO full flag
1 Full
0 Not full
0
R
D0
i2sFiFoeF0 I2S CH.0 FIFO empty flag
1 Empty
0 Not empty
1
R
i2s interrupt
Mode select
Register
(pi2s_int_Mod)
0x00301C18
(32 bits)
D31–8 –
reserved
–
0 when being read.
D7–6 i2sintMd1
[1:0]
I2S CH.0 interrupt mode select
0x3
0x2
0x1
0x0
Reserved
One data
Whole full
Half full
0
R/W
D5
i2shsMd1 I2S CH.1 HSDMA mode select 1 dual
channels
0 single
channel
0
R/W
D4
i2sinten1 I2S CH.1 interrupt enable
1 Enable
0 Disable
0
R/W
D3–2 i2sintMd0
[1:0]
I2S CH.0 interrupt mode select
0x3
0x2
0x1
0x0
Reserved
One empty
Whole empty
Half empty
0
R/W
D1
i2shsMd0 I2S CH.0 HSDMA mode select 1 dual
channels
0 single
channel
0
R/W
D0
i2sinten0 I2S CH.0 interrupt enable
1 Enable
0 Disable
0
R/W
i2s Ch.0 FiFo
Register
(pi2s_FiFo_
Ch0)
0x00301C20
(32 bits)
D31–0 i2sFiFo0
[31:0]
I2S CH.0 FIFO (output data)
0 to 0xffffffff (32 bits)
0x0
W For 16-bit data (word
write) or 24-bit data
(word write)
0 when being read.
0x00301C20
(16 bits)
D15–0 i2sFiFo0
[15:0]
0 to 0xffff (16 bits)
For 16-bit data (half-
word write)
0 when being read.
0x00301C22
(16 bits)
D15–0 i2sFiFo0
[31:16]
i2s Ch.1 FiFo
Register
(pi2s_FiFo_
Ch1)
0x00301C30
(32 bits)
D31–0 i2sFiFo1
[31:0]
I2S CH.1 FIFO (input data)
0 to 0xffffffff (32 bits)
0x0
R For 16-bit data (word
read) or 24-bit data
(word read)
0x00301C30
(16 bits)
D15–0 i2sFiFo1
[15:0]
0 to 0xffff (16 bits)
For 16-bit data (half-
word read)
0x00301C32
(16 bits)
D15–0 i2sFiFo1
[31:16]