
V PeRiPheRaL MoDuLes 3 (inteRFaCe): GeneRaL-PuRPose seRiaL inteRFaCe (eFsio)
s1C33L17 teChniCaL ManuaL
ePson
V-1-43
V
EFSIO
0x300B02–0x300B12: serial i/F Ch.x status Registers (peFsiFx_status)
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
RXDxnuM1
RXDxnuM0
tenDx
FeRx
PeRx
oeRx
tDBex
RDBFx
D7
D6
D5
D4
D3
D2
D1
D0
Number of Ch.x receive data
in FIFO
Ch.x transmit-completion flag
Ch.x framing error flag
Ch.x parity error flag
Ch.x overrun error flag
Ch.x transmit data buffer empty
Ch.x receive data buffer full
0
1
0
R
R/W
R
Reset by writing 0.
00300B02
|
00300B12
(B)
1 Error
0 Normal
1 Transmitting 0 End
1 Error
0 Normal
1 Error
0 Normal
1 Empty
0 Not empty
1 Full
0 Not full
serial i/F Ch.x
status register
(pEFSIFx_STATUS)
1
0
1
0
1
0
RXDxNUM[1:0] Number of data
4
3
2
1 or 0
note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 1.
0x300B02
Serial I/F Ch.0 Status Register (pEFSIF0_STATUS)
0x300B12
Serial I/F Ch.1 Status Register (pEFSIF1_STATUS)
D[7:6]
RXDxnuM[1:0]: number of Ch.x Receive Data in FiFo
Indicates the number of data in the receive data buffer (FIFO) that have not been read.
Table V.1.8.2 Number of Receive Data
RXDxnuM1
1
0
RXDxnuM0
1
0
1
0
number of data
4
3
2
1 or 0
(Default: 0b00)
When RXDxNUM[1:0] is 0, it indicates that the receive data buffer contains 0 or 1 received data. When
RXDxNUM[1:0] is 1 to 3, it indicates that the receive data buffer contains 2 to 4 received data.
D5
tenDx: serial i/F Ch.x transmit-Completion Flag
Indicates the transmission status.
1 (R):
During transmitting
0 (R):
End of transmission (default)
TENDx goes 1 when data is being transmitted and goes 0 when the transmission has completed.
When data is transmitted successively in clock-synchronized master mode or asynchronous mode,
TENDx maintains 1 until all data is transmitted (see Figure V.1.3.3.1 and Figure V.1.4.3.1). In clock-
synchronized slave mode, TENDx goes 0 every time 1-byte data is transmitted (see Figure V.1.3.3.2).
D4
FeRx: serial i/F Ch.x Framing error Flag
Indicates whether a framing error occurred.
1 (R):
An error occurred
0 (R):
No error occurred (default )
1 (W):
Has no effect
0 (W):
Reset to 0
FERx is an error flag indicating whether a framing error occurred. When an error has occurred, it is
set to 1. A framing error occurs when data with a stop bit = 0 is received in ISO7816 or asynchronous
mode.
FERx is reset by writing 0 or when RXENx and TXENx both are set to 0.