
is1C33L17sPeCifiCations:PreCautionsonMounting
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I.9 Precautions on Mounting
The following shows the precautions when designing the board and mounting the IC.
oscillationCircuit
Oscillation characteristics change depending on conditions such as components used (oscillator, Rf, Rd, CG,
CD) and board pattern. In particular, when a ceramic or crystal oscillator is used, evaluate the components
adequately under real operating conditions by mounting them on the board before the external register (Rf, Rd)
and capacitor (CG, CD) values are finally decided.
Disturbances of the oscillation clock due to noise may cause a malfunction. To prevent this, the following
points should be taken into consideration. In particular, the latest devices are more sensitive to noise, as they are
more finely processed.
The measures against noise for the RTC_CLKO pin, and the components and lines connected to this pin is most
essential, and similar measures must also be taken for the RTC_CLKI pin. The measures for the RTC_CLKI
and RTC_CLKO pins are described below.
We recommend taking measures similar to those for the high-speed oscillation system, including the MCLKI
and MCLKO pins and the components and lines connected to these pins.
(1) Components that are connected to the RTC_CLKI and RTC_CLKO pins, such as oscillators, resistors, and
capacitors, should be connected in the shortest line.
(2) Whenever possible, configure digital signal lines with at least three millimeters clearance from the
RTC_CLKI and RTC_CLKO pins and the components and lines connected to these pins. In particular,
signals that are switched frequently must not be placed near these pins, components, and lines. The same
applies to all layers on the multi-layered board as the distance between the layers is around 0.1 to 0.2 mm.
Furthermore, do not configure digital signal lines in parallel with these components and lines when
arranging them on the same or another layer of the board. Such an arrangement is strictly prohibited,
even with clearance of three millimeters or more. Also, avoid arranging digital signal lines across these
components and signal lines.
(3) Shield the RTC_CLKI and RTC_CLKO pins and lines connected to
those pins as well as the adjacent layers of the board using VSS.
As shown in the figure on the right, shield the wired layers as much as
possible.
Whenever possible, make the whole adjacent layers the ground layers,
or ensure there is adequate shielding to a radius of five millimeters
around the above pins and lines.
As described in (2), do not configure digital signal lines in parallel with
components and lines even if such precautionary measures are taken,
and avoid configuring signal lines that are switched frequently across
components and lines on other layers.
(4) When an external clock is supplied to the RTC_CLKI or MCLKI pin, the clock source should be connected
to the RTC_CLKI or MCLKI pin in the shortest line. Furthermore, do not connect anything else to the
RTC_CLKO or MCLKO pin.
(5) After taking the above precautions, check the output clock waveform while operating the actual application
program in the actual device.
To do this, measure the output of the CMU_CLK pins with an oscilloscope.
Check the waveform quality at the OSC3 or PLL output clock by measuring the CMU_CLK output. Ensure
that the frequencies are as designed and that there is no noise or jitters.
Check the waveform quality at the OSC1 clock by measuring the CMU_CLK output (after switching the
system clock source to OSC1). Scale up the ranges around the rising and falling edges of the clock pulse to
ensure that there is no noise, such as clock and spike, in the 100 ns ranges.
RTC_CLKI
RTC_CLKO
VSS
Sample VSS pattern
RTC_CLKI and RTC_CLKO