
iVPeRiPheRaLMoDuLes2(tiMeRs):16-bittiMeRs(t16)
s1C33L17teChniCaLManuaL
ePson
iV-1-7
IV
T16
TableIV.1.5.2DivisionRatio
P16tsx2
1
0
P16tsx1
1
0
1
0
Divisionratio
MCLK/4096
MCLK/1024
MCLK/256
MCLK/64
MCLK/16
MCLK/4
MCLK/2
MCLK/1
P16tsx0
1
0
1
0
1
0
1
0
(Default:0b000=MCLK/1)
notes: Whensettingacountclock,makesurethe16-bittimeristurnedoff.
P16TONx(D3/0x3007E0+2x)forunusedtimersshouldbesetto0toreducecurrentconsumption.
eternalclock
When using the timer as an event counter by supplying clock pulses from an external source, make sure the
event cycle is at least two CPU operating clock cycles.
selectingcomparisondataregister/buffer
The comparison data registers A and B are used to store the data to be compared with the content of the up-
counter. This register can be directly read and written. Furthermore, comparison data can be set via the
comparison register buffer. In this case, the set value is loaded to the comparison data register when the counter
is reset by the comparison match B signal or software (by writing 1 to PRESETx (D1/0x300786 + 8x)).
Select whether comparison data is written to the comparison data register or the buffer using SELCRBx (D5/
0x300786 + 8x).
seLCRbx:16-bitTimerxComparisonRegisterBufferEnableBitinthe16-bitTimerxControlRegister
(D5/0x300786+8x)
When 1 is written to SELCRBx (D5/0x300786 + 8x), the comparison register buffer is selected and when 0 is
written, the comparison data register is selected.
At initial reset, the comparison data register is selected.
settingcomparisondata
The timer contains two data comparators that allows the count data to be compared with given values.
CRxA[15:0] (D[15:0]/0x300780 + 8x) and CRxB[15:0] (D[15:0]/0x300782 + 8x) are used to set these values.
CRxa[15:0]:16-bitTimerxComparisonDataABitsinthe16-bitTimerxComparisonDataASetupRegister
(D[15:0]/0x300780+8x)
CRxb[15:0]:16-bitTimerxComparisonDataBBitsinthe16-bitTimerxComparisonDataBSetupRegister
(D[15:0]/0x300782+8x)
When SELCRBx (D5/0x300786 + 8x) is set to 0, these registers allow direct reading/writing from/to the
comparison data register.
When SELCRBx is set to 1, these registers are used to read/write from/to the comparison register buffer. The
content of the buffer is loaded to the comparison data register when the counter is reset.
At initial reset, the comparison data registers/buffers are not initialized.
The timer compares the comparison data register and count data and, when the two values are equal, generates
a comparison match signal. This comparison match signal controls the clock output (TMx signal) to external
devices, in addition to generating an interrupt.
The comparison data B is also used to reset the counter.