
V PeRiPheRaL MoDuLes 3 (inteRFaCe): asYnChRonous seRiaL tRansCeiVeR (uaRt)
s1C33L17 teChniCaL ManuaL
ePson
V-2-17
V
UART
0x00300B22 : uaRt status Register (uaRt_status)
Register name
address
Bit
name
Function
setting
init. R/W
Remarks
uaRt status
Register
(uaRt_status)
0x00300B22
(8)
D7
–
reserved
–
0 when being read.
D6
FeR
Framing error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D5
PeR
Parity error flag
1 Error
0 Normal
0
R/W
D4
oeR
Overrun error flag
1 Error
0 Normal
0
R/W
D3
RD2B
Second byte receive flag
1 Ready
0 Empty
0
R
D2
tRBs
Transmit busy flag
1 Busy
0 Idle
0
R
Shift register status
D1
RDRY
Receive data ready flag
1 Ready
0 Empty
0
R
D0
tDBe
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
D7
Reserved
D6
FeR: Framing error Flag
Indicates whether a framing error has occurred or not.
1 (R):
An error has occurred
0 (R):
No error has occurred (default)
1 (W):
Reset to 0
0 (W):
Has no effect
When a framing error has occurred, FER is set to 1. A framing error occurs when data with a stop bit =
0 is received.
FER is reset by writing 1 or when RXEN (D0/UART_CTL register) is set to 0.
D5
PeR: Parity error Flag
Indicates whether a parity error has occurred or not.
1 (R):
An error has occurred
0 (R):
No error has occurred (default)
1 (W):
Reset to 0
0 (W):
Has no effect
When a parity error has occurred, PER is set to 1. The parity check function is effective only when
PREN (D3/UART_CFG register) is set to 1. This check is performed when the received data is
transferred from the shift register to the receive data buffer.
PER is reset by writing 1 or when RXEN (D0/UART_CTL register) is set to 0.
D4
oeR: overrun error Flag
Indicates whether an overrun error has occurred or not.
1 (R):
An error has occurred
0 (R):
No error has occurred (default)
1 (W):
Reset to 0
0 (W):
Has no effect
When an overrun error has occurred, OER is set to 1. An overrun error will occur if new data is received
when the receive data buffer is full and also if the shift register contains received data. When this error
occurs, the shift register is overwritten with the new received data. The receive data in the buffer is left
unchanged.
OER is reset by writing 1 or when RXEN (D0/UART_CTL register) is set to 0.
D3
RD2B: second Byte Received Flag
Indicates that the receive data buffer contains two received data.
1 (R):
Second byte is ready to read out
0 (R):
Second entry is empty (default)
RD2B is set to 1 when the second data is loaded to the receive data buffer, and is reset to 0 when the
first data is read out from the receive data buffer.