
aPPendix a i/o MaP
s1C33L17 teChniCaL ManuaL
ePson
aP-a-7
AP
I/Omap
0x300294–0x300298
interrupt Controller
name
address
Register name
Bit
Function
setting
init. R/W
Remarks
de16tC0
de16tu0
dehdM1
dehdM0
deP3
deP2
deP1
deP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
HSDMA Ch.1
HSDMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
00300294
(B)
1 IDMA
enabled
0 IDMA
disabled
Port input 0–3,
hsdMa Ch.0–1,
16-bit timer 0
idMa enable
register
(pIDMAEN_DEP03
_DEHS_DE16T0)
–
de16tC3
de16tu3
de16tC2
de16tu2
de16tC1
de16tu1
D7–6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
–
0
–
R/W
0 when being read.
00300295
(B)
1 IDMA
enabled
0 IDMA
disabled
16-bit timer 1–3
idMa enable
register
(pIDMAEN
_DE16T13)
–
destx0
desRx0
–
D7
D6
D5–0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
reserved
0
–
R/W
–
0 when being read.
00300296
(B)
1 IDMA
enabled
0 IDMA
disabled
serial i/F Ch.0
idMa enable
register
(pIDMAEN
_DESIF0)
–
deP7
deP6
deP5
deP4
–
deade
destx1
desRx1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D conversion completion
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
–
0
R/W
–
R/W
0 when being read.
00300297
(B)
1 IDMA
enabled
0 IDMA
disabled
1 IDMA
enabled
0 IDMA
disabled
–
serial i/F Ch.1,
a/d,
port input 4–7
idMa enable
register
(pIDMAEN_DESIF1
_DEAD_DEP47)
hsd1s3
hsd1s2
hsd1s1
hsd1s0
hsd0s3
hsd0s2
hsd0s1
hsd0s0
D7
D6
D5
D4
D3
D2
D1
D0
HSDMA Ch.1 trigger set-up
HSDMA Ch.0 trigger set-up
0
R/W
00300298
(B)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Software trigger
#DMAREQ1 input (falling edge)
#DMAREQ1 input (rising edge)
Port 1 input
Port 5 input
(reserved)
16-bit timer 1 compare B
16-bit timer 1 compare A
(reserved)
I2S Output Ch. HSDMA Right
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
Port 9 input (USB PDREQ)
Port 13 input
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Software trigger
#DMAREQ0 input (falling edge)
#DMAREQ0 input (rising edge)
Port 0 input
Port 4 input
(reserved)
16-bit timer 0 compare B
16-bit timer 0 compare A
(reserved)
I2S Output Ch. HSDMA Left
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
Port 8 input (SPI interrupt)
Port 12 input
hsdMa Ch.0–1
trigger set-up
register
(pHSDMA_HTGR1)