
is1C33L17sPeCifiCations:overview
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highspeedBus(hB)Modules
sraMC(sraMController)
25-bit address lines and 8/16-bit selectable data bus
UP to a 512M-byte (A[24:0]) address space is provided for each chip enable signal.
Max. 8 chip enable signals are available to connect external devices.
Programmable bus wait cycle (0 to 7 cycles)
Supports external wait signals.
4GB physical address space is available.
- The physical address space is divided into 23 areas: Area 0 to Area 22.
- Areas 0 to 4 and Area 6 are system reserved.
Supports only Little-Endian access to each area.
Memory mapped I/O
Supports both A0 and BS (Bus Strobe) access type external devices.
SRAM, ROM, and Flash ROM direct access interfaces are built in.
sDraMC(sDraMControllerwithsDraMaPPandahBLocalBusarbiter)
Supports SDRAM direct interface.
Supports only SDRAM devices with 16-bit data bus.
Minimum configuration: 16M bits (2MB), 16-bit SDRAM
× 1
Maximum configuration: 512M bits (64MB), 16-bit SDRAM
× 1
CAS latency: 1, 2 or 3 programmable
Supports burst and single read/write.
Supports DQM (byte write) function.
Supports max. 4 SDRAM banks and bank active mode.
Incorporates a 12-bit auto-refresh counter.
Intelligent self-refresh function for low power operation
2-stage
× 32-bit data buffer and 8-stage × 16-bit × 2-slot instruction buffer built-in
Supports up to 90 MHz SDRAM clock.
- When the CPU clock is 48 MHz, the SDRAM clock can be set to 48 MHz.
- When the CPU clock is 45 MHz, the SDRAM clock can be set to 90 MHz using the PLL.
Arbitrates ownership of the external bus between the CPU, DMAC, LCDC and SRAMC.
DMaC(DirectMemoryaccessController)
4-ch. high speed hardware DMA
128-ch. intelligent DMA (variable data transfer controller) with specific control table
ivraMarB(internalvideoraMarbiter)
Contains a 12KB SRAM (3,072 words
× 16 bits × 2).
Arbitrates accesses from the LCDC and CPU.
Allows the CPU and LCDC to access IVRAM in minimum 2 cycles by 32-bit access.
Supports UMA (Unified Memory Access) for display.
IVRAM is configurable as a 12KB general-purpose RAM in Area 0 using a control register if it is not
used as a video RAM.
PeripheralBus(saPB)Modules
tCu(timer/CounterunitwithPwMoutputs)
4-ch. 16-bit timer/counter
Supports PWM outputs with DA16 (Digital D/A) mode.
Contains a prescaler, which can divide the peripheral clock by 1 to 4,096, to generate the operating clock
for each channel.
Possible to invoke DMA transfer.
wDt(watchdogtimer)
30-bit watchdog timer to generate an NMI interrupt
The watchdog timer overflow cycle (NMI interrupt cycle) is programmable.
The watchdog timer overflow signal can be output outside the IC.