
iiBusModuLes:inteLLigentdMa(idMa)
s1C33L17teChniCaLManuaL
ePson
ii-2-19
II
IDMA
0x301100:idMaBaseaddressRegister0(pidMaBase)
0x301102:idMaBaseaddressRegister1
name
address
Registername
Bit
Function
setting
init. R/W
Remarks
dBaseL15
dBaseL14
dBaseL13
dBaseL12
dBaseL11
dBaseL10
dBaseL9
dBaseL8
dBaseL7
dBaseL6
dBaseL5
dBaseL4
dBaseL3
dBaseL2
dBaseL1
dBaseL0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IDMAbaseaddress
low-order16bits
(Initialvalue:0x200003A0)
0
1
0
1
0
R/W
Fixat0.
00301100
(hW)
idMa
baseaddress
register0
(pIDMABASE)
dBaseh15
dBaseh14
dBaseh13
dBaseh12
dBaseh11
dBaseh10
dBaseh9
dBaseh8
dBaseh7
dBaseh6
dBaseh5
dBaseh4
dBaseh3
dBaseh2
dBaseh1
dBaseh0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IDMAbaseaddress
high-order16bits
(Initialvalue:0x200003A0)
0
1
0
R/W
00301102
(hW)
idMa
baseaddress
register1
Specify the starting address of the control information to be placed in RAM.
At initial reset, the base address is set to 0x200003A0.
d[15:0]/0x301100dBaseL[15:0]:idMaLow-orderBaseaddressBits
Use DBASEL to set the 16 low-order bits of the base address.
d[15:0]/0x301102dBaseh[15:0]:idMahigh-orderBaseaddressBits
Use DBASEH to set the 16 high-order bits of the base address.
In the S1C33L17 IDMA, the DBASEH[15:12] bits have been added to extend the base address into 32
bits.
notes: ThecontrolinformationmustbeplacedinDSTRAM(area3)oranexternalRAM.A0RAM(area
0)cannotbeusedtostorecontrolinformation.
The address you set in the IDMA base address registers must always be 4-word units
boundaryaddress.
Theseregisterscannotbereadorwritteninbytes.Theregistersmustbeaccessedinwords
for read/write operations to address 0x301100, or in half-words for read/write operations to
addresses 0x301100 and 0x301102.Write operations in half-words must be performed in
order of 0x301100 and 0x301102. Read operations in half-words may be performed in any
order.
Be sure to disable DMA transfers (IDMAEN (D0/0x301105) = 0) before setting the base
address.Writing to the IDMA base address register is ignored when the DMA transfer
is enabled (IDMAEN (D0/0x301105) = 1).When the register is read, the read data is
indeterminate.