
aPPenDiX e SuMMaRY OF PReCauTiOnS
S1C33L17 TeChniCaL ManuaL
ePSOn
aP-e-7
AP
Notes
When the transmit-enable bit TXENx is set to 0 to disable transmit operations, the transmit data buffer (FIFO)
is cleared (initialized). Similarly, when the receive-enable bit RXENx is set to 0 to disable receive operations,
the receive data buffer (FIFO) is cleared (initialized). Therefore, make sure that the buffer does not contain
any data waiting for transmission or reading before writing 0 to these bits.
During IrDA receive operations, the RZI circuit recognizes low pulses by means of the signal edge (rising
edge when IRRLx = 0; falling edge when IRRLx = 1). Note that noise may cause a malfunction.
iRRLx: Serial I/F Ch.x IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.x IrDA Register (D2/0x300Bx4)
Serial Peripheral interface (SPi)
Be sure to use 32-bit access instructions for reading/writing from/to the SPI control registers (0x301700 to
0x30171C). The SPI control registers do not allow reading/writing using 16-bit and 8-bit access instructions.
Do not access the SPI Control Register 1 (0x301708), SPI Control Register 2 (0x30170C), and SPI Wait
Register (0x301710) while the BSYF (D6/0x301714) is set to 1 (during data transfer).
BSYF: Transfer Busy Flag in the SPI Status Register (D6/0x301714)
To prevent malfunctions, write 0x0 to the SPI Interrupt Control Register (0x301718) to disable all the SPI
interrupt requests, before disabling the SPI circuit (before setting ENA (D0/0x301708) to 0).
ena: SPI Enable Bit in the SPI Control Register 1 (D0/0x301708)
Card interface (CaRD)
The interface supports 16-bit PC cards, such as ATA (CF), LAN (Ethernet, wireless), or modem connected as
an I/O card. SRAM cards, etc. are not supported.
Live or hot-line card insertion and removal are not supported. Power must be turned off before inserting or
removing a card. The automatic recognition of cards is also not supported.
DMA, ZV, and CardBus are also not supported.
To accommodate differences in power supply voltage between the PC card (5 V or 3.3 V) and the S1C33L17,
use a buffer IC (e.g., S1C37120).
The EDC generator supports only one data organization mode: 512-byte
× 8-bit mode.
The card I/O signals must be connected to the D[15:0] pins when using the EDC function.
EDCRST (D0/0x300311) should be set before using the EDC function.
eDCRST: EDC Circuit Reset Bit in the EDC Reset/Ready Register (D0/0x300311)
The EDCEN (D0/0x300312) should be set only while reading or writing card data. It should be disabled
during command input, address input or status reading.
eDCen: EDC Circuit Enable Bit in the EDC Enable Register (D0/0x300312)