
iVPeRiPheRaLMoDuLes2(tiMeRs):WatChDogtiMeR(WDt)
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ePson
iV-2-11
IV
WDT
0300664:WatchdogtimerComparisonDatasetupRegister0(pWD_CoMP_LoW)
0300666:WatchdogtimerComparisonDatasetupRegister1(pWD_CoMP_high)
name
address
Registername
bit
Function
setting
init. R/W
Remarks
0x0to0x3FFFFFFF
(low-order16bits)
CMPDt15
CMPDt14
CMPDt13
CMPDt12
CMPDt11
CMPDt10
CMPDt9
CMPDt8
CMPDt7
CMPDt6
CMPDt5
CMPDt4
CMPDt3
CMPDt2
CMPDt1
CMPDt0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Watchdogtimercomparisondata
CMPDT0=LSB
0
R/W
00300664
(hW)
Watchdog
timer
comparison
datasetup
register0
(pWD_COMP_LOW)
–
0x0to0x3FFFFFFF
(high-order14bits)
–
CMPDt29
CMPDt28
CMPDt27
CMPDt26
CMPDt25
CMPDt24
CMPDt23
CMPDt22
CMPDt21
CMPDt20
CMPDt19
CMPDt18
CMPDt17
CMPDt16
D15–14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Watchdogtimercomparisondata
CMPDT29=MSB
–
0
–
R/W
0whenbeingread.
00300666
(hW)
Watchdog
timer
comparison
datasetup
register1
(pWD_COMP_HIGH)
note: These registers are write-protected to prevent NMI or reset signals from being inadvertently
generatedbyunnecessarywriteoperations.Torewritetheseregisters,writeprotectionmustbe
removedbywriting0x96totheWatchdogTimerWrite-ProtectRegister(0x300660).Oncethereg-
istershavebeenrewritten,besuretowriteotherthan0x96totheWatchdogTimerWrite-Protect
Register(0x300660)toreapplywriteprotection.
Use these registers to set the NMI/reset generation cycle.
With NMI or reset generation enabled, an NMI or reset signal is output when the up-counter matches the compari-
son data set in these registers.
When a clock is output from the watchdog timer, these registers also set the output clock cycle.
D[15:0]/0300664CMPDt[15:0]:WatchdogtimerComparisonData(16low-orderbits)
The 16 low-order bits of comparison data are set in these bits. (Default: 0x0000)
D[13:0]/0300666CMPDt[29:16]:WatchdogtimerComparisonData(14high-orderbits)
The 14 high-order bits of comparison data are set in these bits. (Default: 0x0000)
note: Donotsetavalueequaltoorlessthan0x0000001Fascomparisondata.