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G2 PowerPC Core Reference Manual
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MOTOROLA
Implementation-Specific Information
Block address translation (BAT) arrays—The G2_LE core has 16 additional BAT
registers (four pairs of DBAT and IBAT registers).
One additional instruction address breakpoint register (IABR2) and two new data
address breakpoint registers (DABR, DABR2) are added to the G2_LE (not in G2
core).
One instruction breakpoint control (IBCR) and one data breakpoint control (DBCR)
are implemented in the G2_LE core (not in G2 core).
1.3.2
Instruction Set and Addressing Modes
The following sections describe the PowerPC instruction set and addressing modes in
general.
1.3.2.1
PowerPC Instruction Set and Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats
are consistent among all instruction types, permitting efficient decoding to occur in parallel
with operand accesses. This fixed instruction length and consistent format simplifies
instruction pipelining.
The PowerPC instructions are divided into the following categories:
Integer instructions—These include computational and logical instructions.
— Integer arithmetic instructions
— Integer compare instructions
— Integer logical instructions
— Integer rotate and shift instructions
Floating-point instructions—These include floating-point computational
instructions, as well as instructions that affect the FPSCR.
— Floating-point arithmetic instructions
— Floating-point multiply/add instructions
— Floating-point rounding and conversion instructions
— Floating-point compare instructions
— Floating-point status and control instructions
Load/store instructions—These include integer and floating-point load and store
instructions.
— Integer load and store instructions
— Integer load and store multiple instructions
— Floating-point load and store
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