
MOTOROLA
Chapter 3. Instruction Set Model
3-27
Instruction Set Summary
3.2.4.4.3
Condition Register Logical Instructions
Condition register logical instructions, shown in Table 3-22, and the Move Condition
Register Field (
mcrf
) instruction are also defined as flow control instructions, although
they are executed by the system register unit (SRU). Most instructions executed by the SRU
are completion-serialized to maintain system state; that is, the instruction is held for
execution in the SRU until all prior instructions issued have completed.
Note that if the LR update option is enabled for any of these instructions, these forms of the
instructions are invalid in the G2 core.
3.2.4.5
Trap Instructions
The trap instructions shown in Table 3-23 are provided to test for a specified set of
conditions. If any of the conditions tested by a trap instruction are met, the system trap
handler is invoked. If the tested conditions are not met, instruction execution continues
normally.
Table 3-21. Branch Instructions
Name
Mnemonic
Operand Syntax
Branch
b
(
ba
bl
bla
)
target_addr
Branch Conditional
bc
(
bca
bcl
bcla
)
BO
,
BI
,
target_addr
Branch Conditional to Count Register
bcctr
(
bcctrl
)
BO
,
BI
Branch Conditional to Link Register
bclr
(
bclrl
)
BO
,
BI
Table 3-22. Condition Register Logical Instructions
Name
Mnemonic
Operand Syntax
Condition Register AND
crand
crb
D
,crb
A
,crb
B
Condition Register AND with Complement
crandc
crb
D
,crb
A
,crb
B
Condition Register Equivalent
creqv
crb
D
,crb
A
,crb
B
Condition Register NAND
crnand
crb
D
,crb
A
,crb
B
Condition Register NOR
crnor
crb
D
,crb
A
,crb
B
Condition Register OR
cror
crb
D
,crb
A
,crb
B
Condition Register OR with Complement
crorc
crb
D
,crb
A
,crb
B
Condition Register XOR
crxor
crb
D
,crb
A
,crb
B
Move Condition Register Field
mcrf
crf
D
,crf
S
Table 3-23. Trap Instructions
Name
Mnemonic
Operand Syntax
Trap Word
tw
TO
,r
A
,r
B
Trap Word Immediate
twi
TO
,r
A
,
SIMM
F
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