
Glossary-14
G2 PowerPC Core Reference Manual
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MOTOROLA
in the CQ at the same time they are passed to the execute stage. They
can be said to occupy both the complete and execute stages in the
same clock cycle.
Stall.
An occurrence when an instruction cannot proceed to the next stage.
Static branch prediction.
Mechanism by which software (for example,
compilers) can hint to the machine hardware about the direction a
branch is likely to take.
Store Queue.
Holds store operations that have not been committed to
memory, resulting from completed or retired instructions.
Superscalar.
A superscalar processor is one that can dispatch multiple
instructions concurrently from a conventional linear instruction
stream. In a superscalar implementation, multiple instructions can be
in the same stage at the same time.
Supervisor mode.
The privileged operation state of a processor. In
supervisor mode, software, typically the operating system, can
access all control registers and can access the supervisor memory
space, among other privileged operations.
Synchronization.
A process to ensure that operations occur strictly
in order
.
See
Context synchronization
and
Execution synchronization
.
Synchronous exception.
An
exception
that is generated by the execution of
a particular instruction or instruction sequence. There are two types
of synchronous exceptions,
precise
and
imprecise
.
System memory.
The physical memory available to a processor.
T
Tenure.
The period of bus mastership. For the G2, there can be separate
address bus tenures and data bus tenures. A tenure consists of three
phases: arbitration, transfer, and termination.
TLB (translation lookaside buffer).
A cache that holds recently-used
page
table entries
.
Throughput.
The measure of the number of instructions that are processed
per clock cycle.
F
Freescale Semiconductor, Inc.
n
.