
3-2
G2 PowerPC Core Reference Manual
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MOTOROLA
Operand Conventions
negation of core_hreset, and should remain unchanged by software for the duration of the
system operation.
Bit 4 of HID2, (HID2[LET]) is used in conjunction with MSR[LE] to indicate the endian
mode of operation of the G2_LE core as shown in Table 3-1.
When the G2_LE core is in true little-endian mode, memory and I/O subsystems are treated
as true little-endian. The following occurs when operating in true little-endian mode:
The byte reversing for instruction occurs before the instruction is decoded.
The byte reversing for data occurs when the data item is being moved to or from the
GPR.
Therefore, the byte reversal in little-endian mode for load or store accesses occurs between
memory or the data cache, and the register files for the G2_LE core.
3.1.3
Alignment and Misaligned Accesses
The operand of a single-register memory access instruction has a natural alignment
boundary equal to the operand length. In other words, the natural address of an operand is
an integral multiple of the operand length. A memory operand is said to be aligned if it is
aligned at its natural boundary; otherwise it is misaligned. For a detailed discussion about
memory operands, see Chapter 3, “Operand Conventions,” in the
Programming
Environments Manual
.
Operands for single-register memory access instructions have the characteristics shown in
Table 3-2. (Although not permitted as memory operands, quad words are shown because
quad-word alignment is desirable for certain memory operands.)
Table 3-1. Endian Mode Indication
MSR[LE]
HID2[LET]
Endian Mode
0
x
Big-endian
1
0
Modified (PowerPC) little-endian
1
1
True little-endian
F
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n
.