
5-8
G2 PowerPC Core Reference Manual
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Exception Classes
5.1.2
Summary of Front-End Exception Handling
The following list of interrupt categories describes how the G2 core handles exceptions up
to the point of signaling the appropriate exception to occur. Note that a recoverable state is
reached if the completed store queue is empty (drained, not canceled) and any instruction
that is next in program order and has been signaled to complete has completed. If MSR[RI]
is clear, the core is in a nonrecoverable state by default. Also, completion of an instruction
is defined as performing all architectural register writes associated with that instruction,
and then removing that instruction from the completion buffer queue.
Asynchronous nonmaskable nonrecoverable—(system reset caused by the assertion
of either core_hreset or internally during power-on reset (POR)). These exceptions
have highest priority and are taken immediately regardless of other pending
exceptions or recoverability. A nonpredicted address is guaranteed.
Asynchronous maskable nonrecoverable—(machine check). A machine check
exception takes priority over any other pending exception except a nonrecoverable
system reset caused by the assertion of either core_hreset or internally during POR.
A machine check exception is taken immediately regardless of recoverability. A
machine check exception can occur only if the machine check enable bit, MSR[ME],
is set. If MSR[ME] is cleared, the processor goes directly into checkstop state when
a machine check exception condition occurs. A nonpredicted address is guaranteed.
Asynchronous nonmaskable recoverable—(system reset caused by the assertion of
core_sreset). This interrupt takes priority over any other pending exceptions except
nonrecoverable exceptions listed above. This exception is taken immediately when
a recoverable state is reached.
Asynchronous maskable recoverable—(system management interrupt, critical
interrupt (G2_LE only), external interrupt, decrementer exception). Before handling
this type of exception, the next instruction in program order must complete or
except. If this action causes another type of exception, that exception is taken and
the asynchronous maskable recoverable exception remains pending. Once an
instruction can complete without causing an exception, further instruction
completion is halted while the exception not taken remains pending. The exception
is taken when a recoverable state is reached.
Instruction fetch—(ITLB, ISI). When this type of exception is detected, dispatch is
halted and the current instruction stream is allowed to drain. If completing any
instructions in this stream causes an exception, that exception is taken and the
instruction fetch exception is forgotten. Otherwise, as soon as the machine is empty
and a recoverable state is reached, the instruction fetch exception is taken.
Instruction dispatch/execution—(program, DSI, alignment, emulation trap, system
call, DTLB miss on load or store, IABR). This type of exception is determined at
dispatch or execution of an instruction. The exception remains pending until all
instructions in program order before the exception-causing instruction are
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