
MOTOROLA
Chapter 4. Instruction and Data Cache Operation
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4-15
Cache Coherency—MEI Protocol
No errors except machine check exceptions are reported due to the out-of-order
execution of an instruction until it is known that execution of the instruction is
required.
Machine check exceptions resulting solely from out-of-order execution (from nonguarded
memory) may be reported. When an out-of-order instruction result is abandoned, only one
side effect (other than a possible machine check) may occur—the referenced bit (R) in the
corresponding page table entry (and TLB entry) can be set due to an out-of-order load
operation. See Chapter 5, “Exceptions,” for more information on the machine check
exception.
Thus, an out-of-order load or store instruction will not access guarded memory unless one
of the following conditions exist:
The target memory item is resident in an on-chip cache. In this case, the location
may be accessed from the cache or main memory.
The target memory item is cacheable (I = 0) and it is guaranteed that the load or store
is in the execution path (assuming there are no intervening exceptions). In this case,
the entire cache block containing the target may be loaded into the cache.
4.6.5.3
Effects of Out-of-Order Instruction Fetches
To avoid instruction fetch delay, the processor typically fetches instructions ahead of those
currently being executed. Such instruction prefetching is said to be out-of-order in that
prefetched instructions may not be executed due to intervening branches or exceptions.
During instruction prefetching, no errors except machine check exceptions are reported due
to the out-of-order fetching of an instruction until it is known that execution of the
instruction is required.
Machine check exceptions resulting solely from out-of-order execution (from nonguarded
memory) may be reported. When an out-of-order instruction result is abandoned, only one
side effect (other than a possible machine check) may occur—the referenced bit (R) in the
corresponding page table entry (and TLB entry) can be set due to an out-of-order load
operation. See Chapter 5, “Exceptions,” for more information on the machine check
exception.
Instruction fetching from guarded memory is not permitted.
4.7
Cache Coherency—MEI Protocol
The primary objective of a coherent memory system is to provide the same image of
memory to all devices using the system. Coherency allows synchronization and cooperative
use of shared resources. Otherwise, multiple copies of a memory location, some containing
stale values, could exist in a system resulting in errors when the stale values are used. Each
potential bus master must follow rules for managing the state of its cache.
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