
MOTOROLA
Chapter 4. Instruction and Data Cache Operation
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4-29
MEI State Transactions
For additional information about the G2 core bus interface and the bus protocols, refer to
Chapter 9, “Core Interface Operation.”
4.11 MEI State Transactions
Table 4-8 shows MEI state transitions for various operations. Bus operations are described
in Table 4-6.
Table 4-8. MEI State Transitions
Operation
Cache
Operation
Bus
Sync
WIM
Current
State
Next
State
Cache Actions
Bus Operation
Load
(T = 0)
Read
No
x0x
I
Same
1 Cast out of modified
block (as required)
Write-with-kill
2 Pass four-beat read to
memory queue
Read
Load
(T = 0)
Read
No
x0x
E,M
Same
Read data from cache
—
Load (T = 0)
Read
No
x1x
I
Same
Pass single-beat read to
memory queue
Read
Load (T = 0)
Read
No
x1x
E
I
CRTRY read
—
Load (T = 0)
Read
No
x1x
M
I
CRTRY read (push sector
to write queue)
Write-with-kill
lwarx
Read
Acts like other reads but bus operation uses special encoding
Store
(T = 0)
Write
No
00x
I
Same
1 Cast out of modified
block (if necessary)
Write-with-kill
2 Pass RWITM to
memory queue
RWITM
Store
(T = 0)
Write
No
00x
E,M
M
Write data to cache
—
Store
≠
stwcx.
(T = 0)
Write
No
10x
I
Same
Pass single-beat write to
memory queue
Write-with-flush
Store
≠
stwcx.
(T = 0)
Write
No
10x
E
Same
1 Write data to cache
—
2 Pass single-beat write
to memory queue
Write-with-flush
Store
≠
stwcx.
(T = 0)
Write
No
10x
M
Same
1 CRTRY write
—
2 Push block to write
queue
Write-with-kill
Store (T = 0)
or
stwcx.
(WIM = 10x)
Write
No
x1x
I
Same
Pass single-beat write to
memory queue
Write-with-flush
Store (T = 0)
or
stwcx.
(WIM = 10x)
Write
No
x1x
E
I
CRTRY write
—
F
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