
5-24
G2 PowerPC Core Reference Manual
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MOTOROLA
Exception Definitions
5.5.2.2
Checkstop State (MSR[ME] = 0)
When the G2 core enters the checkstop state, it asserts the checkstop output signal,
core_ckstp_out. The following events cause the G2 core to enter the checkstop state:
Machine check exception occurs with MSR[ME] cleared
External checkstop input, core_ckstp_in, is asserted.
When a processor is in the checkstop state, instruction processing is suspended and
generally cannot be restarted without resetting the processor. The contents of all latches are
frozen within two cycles upon entering the checkstop state so that the state of the processor
can be analyzed as an aid in problem determination.
Note that not all processors that implement the PowerPC architecture provide the same
level of error checking. The reasons a processor can enter checkstop state are
implementation-dependent.
5.5.3
DSI Exception (0x00300)
A DSI exception occurs when no higher priority exception exists and a data memory access
cannot be performed. The condition that caused the DSI exception can be determined by
reading the DSISR register, a supervisor-level SPR (SPR18) that can be read by using the
mfspr
instruction. Bit settings are provided in Table 5-14. Table 5-14 also indicates the
memory element that is saved to the DAR.
Table 5-13. Machine Check Exception—Register Settings
Register
Setting Description
SRR0
Set to the address of the next instruction that would have been completed in the interrupted instruction
stream. Neither this instruction nor any others beyond it will have been completed. All preceding
instructions will have been completed.
SRR1
0–11
12
13
14
15
16–31 Loaded from MSR[16–31]
Cleared
core_mcp—Machine check signal caused exception
core_tea—Transfer error acknowledge signal caused exception
core_dpe—Data parity error condition (and signal assertion) caused exception
core_ape—Address parity error condition (and signal assertion) caused exception
MSR
POW 0
TGPR 0
ILE
EE
PR
—
0
0
FP
ME
FE0
SE
BE
0
—
0
0
0
FE1
CE
IP
IR
DR
0
0
—
0
0
RI
LE
0
Set to value of ILE
Note:
When a machine check exception is taken, the exception handler should set MSR[ME] as soon as it is practical
to handle another core_tea assertion. Otherwise, subsequent core_tea assertions cause the processor to
automatically enter the checkstop state.
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