
Index-6
G2 PowerPC Core Reference Manual
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MOTOROLA
I–I
Illegal instruction class, 3-7
ILOCK, 4-5
ILOCK control bit, 4-5
IMMU, 6-25
Indeterminate processor core state, 11-8
Input/output enable and high-impedance control signals,
8-3
Instruction accesses, 6-1
Instruction address breakpoint
control register (IBCR), 2-10
examples, 11-6
exception, 5-37, 11-2, 11-3, 11-4
exception handler, 11-2, 11-8
registers, 11-1
Instruction address translation, 2-7
instruction block address translation, 4-35, 4-39
Instruction cache
cache control bits, 4-4
cache fill operations, 4-4
configuration, 4-2
organization, 4-4
Instruction cache enable, 2-12
Instruction cache flash invalidate, 2-12
Instruction cache lock, 2-12
Instruction cache way-lock, 2-15
Instruction queue, 7-8
Instruction timing
examples
cache hit, 7-11, 7-14
execution unit, 7-16
instruction flow, 7-8
memory performance considerations, 7-22
overview, 1-32, 7-3
terminology, 7-1
Instruction TLB miss exception, 5-36
Instruction translation miss, 5-5
Instruction unit, 1-8
Instructional address control register (IBCR), 11-2
Instructions
branch address calculation, 3-26
branch instructions, 3-26, A-22
cache management instructions, 3-31, 3-35, 4-22,
A-23
classes, 3-6
condition register logical, 3-27, A-22
defined instructions, 3-7
external control, 3-32, A-24
floating-point
arithmetic, 3-16, A-18
compare, 3-17, A-19
FP load instructions, 3-24, A-21
FP move instructions, 3-18, A-22
FP status and control register, 3-18
FP store instructions, 3-25, A-21
FPSCR isntructions, 3-18, A-19
multiply-add, 3-16, A-18
rounding and conversion, 3-17, A-18
G2-specific instructions, 3-37
illegal instructions, 3-7
integer
arithmetic, 3-12, A-15
compare, 3-13, A-16
load, A-19
logical, 3-13, A-16
multiple, 3-22, A-20
rotate and shift, 3-14, A-17
store, 3-20, A-20
latency summary, 7-26
load and store
address generation, floating-point, 3-24
address generation, integer, 3-19
byte-reverse instructions, 3-21, A-20
integer load, 3-20
integer multiple instructions, 3-22, A-20
integer store, 3-20
string instructions, 3-23, A-21
memory control, 3-31, 3-35, 4-22, A-23
memory synchronization, 3-28, 3-30, A-21
PowerPC instructions, list
form (format), A-25
function, A-15
legend, A-36
mnemonic, A-1
opcode, A-8
processor control, 3-28, 3-30, 3-33, A-23
reserved instructions, 3-8
segment register manipulation, 3-36, A-24
simplified mnemonics, 3-37
supervisor-level cache management, 3-36
system linkage, 3-33, A-23
TLB management instructions, 3-36, A-24
trap instructions, 3-27, A-23
INT signal, 8-39, 9-41
Integer arithmetic instructions, 3-12, A-15
Integer compare instructions, 3-13, A-16
Integer load instructions, 3-20, A-19
Integer logical instructions, 3-13, A-16
Integer multiple instructions, 3-22, A-20
Integer rotate and shift instructions, 3-14, A-17
Integer store instructions, 3-20, A-20
Integer unit, 7-4
execution timing, 7-20
latency, integer instructions, 7-27
overview, 1-9
Interrupt and checkstop signals, 8-39
Interrupt vector, 10-2
Interrupt, critical, 5-33
Interrupt, external, 5-27
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